MC9S12DP512CPVE Datasheet, PDF (64/124 Pages) Freescale Semiconductor, Inc – MC9S12DP512 Device Guide V01.25

MC9S12DP512 Device Guide V01.25
2.3.55 PS2 / RXD1 — Port S I/O Pin 2
PS2 is a general purpose input or output pin. It can be configured as the receive pin RXD of Serial
Communication Interface 1 (SCI1).
2.3.56 PS1 / TXD0 — Port S I/O Pin 1
PS1 is a general purpose input or output pin. It can be configured as the transmit pin TXD of Serial
Communication Interface 0 (SCI0).
2.3.57 PS0 / RXD0 — Port S I/O Pin 0
PS0 is a general purpose input or output pin. It can be configured as the receive pin RXD of Serial
Communication Interface 0 (SCI0).
2.3.58 PT[7:0] / IOC[7:0] — Port T I/O Pins [7:0]
PT7-PT0 are general purpose input or output pins. They can be configured as input capture or output
compare pins IOC7-IOC0 of the Enhanced Capture Timer (ECT).
2.4 Power Supply Pins
MC9S12DP512 power and ground pins are described below.
Table 2-2 MC9S12DP512 Power and Ground Connection Summary
Pin Number
Mnemonic
112-pin QFP
Nominal
Voltage
Description
V_{DD1, 2}
V_{SS1, 2}
13, 65
14, 66
2.5 V
0V
Internal power and ground generated by internal regulator
V_DDR
41
5.0 V _{External power and ground, supply to pin drivers and internal voltage}
V_SSR
40
0V
regulator.
V_DDX
107
5.0 V
External power and ground, supply to pin drivers.
V_SSX
106
0V
V_DDA
83
5.0 V Operating voltage and ground for the analog-to-digital converters and
the reference for the internal voltage regulator, allows the supply
V_SSA
86
0V
voltage to the A/D to be bypassed independently.
V_RL
85
0V
Reference voltages for the analog-to-digital converter.
V_RH
84
5.0 V
V_DDPLL
43
V_SSPLL
45
2.5 V
0V
Provides operating voltage and ground for the Phased-Locked Loop.
This allows the supply voltage to the PLL to be bypassed
independently. Internal power and ground generated by internal
regulator.
VREGEN
97
5V
Internal Voltage Regulator enable/disable