MC9S12DP512CPVE Datasheet, PDF (53/124 Pages) Freescale Semiconductor, Inc – MC9S12DP512 Device Guide V01.25

2.2 Signal Properties Summary
MC9S12DP512 Device Guide V01.25
Table 2-1 summarizes the pin functionality.
Table 2-1 Signal Properties
Pin Name Pin Name Pin Name Pin Name Pin Name Power
Funct. 1 Funct. 2 Funct. 3 Funct. 4 Funct. 5 Supply
Internal Pull
Resistor
CTRL
Reset
State
Description
EXTAL
—
XTAL
—
—
—
—
VDDPLL
—
—
—
Oscillator Pins
RESET
—
TEST
—
—
—
—
VDDR
External Reset
None None
—
—
—
NA
Test Input
VREGEN
—
—
—
—
VDDX
Voltage Regulator Enable Input
XFC
—
—
—
—
VDDPLL
PLL Loop Filter
BKGD
TAGHI
MODC
—
—
VDDR
Always
Up
Up
Background Debug, Tag High, Mode
Input
PAD15
AN15
ETRIG1
—
—
Port AD Input, Analog Input AN7 of
ATD1, External Trigger Input of ATD1
PAD[14:8] AN[14:08]
—
—
PAD07
AN07
ETRIG0
—
—
Port AD Inputs, Analog Inputs
AN[6:0] of ATD1
VDDA None None
—
Port AD Input, Analog Input AN7 of
ATD0, External Trigger Input of ATD0
PAD[06:00] AN[06:00]
—
—
—
Port AD Inputs, Analog Inputs
AN[6:0] of ATD0
PA[7:0]
ADDR[15:8]/
DATA[15:8]
—
—
—
PB[7:0]
ADDR[7:0]/
DATA[7:0]
—
—
—
PUCR/
PUPAE
Port A I/O, Multiplexed Address/Data
Disabled
PUCR/
PUPBE
Port B I/O, Multiplexed Address/Data
PE7
NOACC
XCLKS
—
—
PUCR/
PUPEE
Up
Port E I/O, Access, Clock Select
PE6
IPIPE1
MODB
—
PE5
IPIPE0
MODA
—
While RESET
—
pin is low:
Port E I/O, Pipe Status, Mode Input
VDDR
Down
While RESET
—
pin is low:
Port E I/O, Pipe Status, Mode Input
Down
PE4
ECLK
—
—
—
Port E I/O, Bus Clock Output
PE3
LSTRB
TAGLO
—
—
PE2
R/W
—
—
—
PE1
IRQ
—
—
—
Port E I/O, Byte Strobe, Tag Low
PUCR/
PUPEE
Up
Port E I/O, R/W in expanded modes
Port E Input, Maskable Interrupt
PE0
XIRQ
—
—
—
Port E Input, Non Maskable Interrupt
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