MC9S12DP512CPVE Datasheet, PDF (73/124 Pages) Freescale Semiconductor, Inc – MC9S12DP512 Device Guide V01.25

Section 5 Resets and Interrupts
MC9S12DP512 Device Guide V01.25
5.1 Overview
Consult the Exception Processing section of the CPU12 Reference Manual for information on resets and
interrupts.
5.2 Vectors
5.2.1 Vector Table
Table 5-1 lists interrupt sources and vectors in default order of priority.
Vector Address
$FFFE, $FFFF
$FFFC, $FFFD
$FFFA, $FFFB
$FFF8, $FFF9
$FFF6, $FFF7
$FFF4, $FFF5
$FFF2, $FFF3
$FFF0, $FFF1
$FFEE, $FFEF
$FFEC, $FFED
$FFEA, $FFEB
$FFE8, $FFE9
$FFE6, $FFE7
$FFE4, $FFE5
$FFE2, $FFE3
$FFE0, $FFE1
$FFDE, $FFDF
$FFDC, $FFDD
$FFDA, $FFDB
$FFD8, $FFD9
$FFD6, $FFD7
$FFD4, $FFD5
$FFD2, $FFD3
$FFD0, $FFD1
$FFCE, $FFCF
$FFCC, $FFCD
Table 5-1 Interrupt Vector Locations
Interrupt Source
CCR
Mask
Local Enable
Reset
None
None
Clock Monitor fail reset
None PLLCTL (CME, SCME)
COP failure reset
None
COP rate select
Unimplemented instruction trap
None
None
SWI
None
None
XIRQ
X-Bit
None
IRQ
I-Bit
IRQCR (IRQEN)
Real Time Interrupt
I-Bit
CRGINT (RTIE)
Enhanced Capture Timer channel 0 I-Bit
TIE (C0I)
Enhanced Capture Timer channel 1 I-Bit
TIE (C1I)
Enhanced Capture Timer channel 2 I-Bit
TIE (C2I)
Enhanced Capture Timer channel 3 I-Bit
TIE (C3I)
Enhanced Capture Timer channel 4 I-Bit
TIE (C4I)
Enhanced Capture Timer channel 5 I-Bit
TIE (C5I)
Enhanced Capture Timer channel 6 I-Bit
TIE (C6I)
Enhanced Capture Timer channel 7 I-Bit
TIE (C7I)
Enhanced Capture Timer overflow
I-Bit
TSRC2 (TOI)
Pulse accumulator A overflow
I-Bit
PACTL (PAOVI)
Pulse accumulator input edge
I-Bit
PACTL (PAI)
SPI0
I-Bit
SPICR1 (SPIE, SPTIE)
SCI0
I-Bit
SCICR2
(TIE, TCIE, RIE, ILIE)
SCI1
I-Bit
SCICR2
(TIE, TCIE, RIE, ILIE)
ATD0
I-Bit
ATDCTL2 (ASCIE)
ATD1
I-Bit
ATDCTL2 (ASCIE)
Port J
I-Bit
PIEJ
(PIEJ7, PIEJ6, PIEJ1, PIEJ0)
Port H
I-Bit
PIEH (PIEH7-0)
HPRIO Value
to Elevate
–
–
–
–
–
–
$F2
$F0
$EE
$EC
$EA
$E8
$E6
$E4
$E2
$E0
$DE
$DC
$DA
$D8
$D6
$D4
$D2
$D0
$CE
$CC
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