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MC9S12DP512CPVE Datasheet, PDF (21/124 Pages) Freescale Semiconductor, Inc – MC9S12DP512 Device Guide V01.25 | |||
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MC9S12DP512 Device Guide V01.25
⢠Inter-IC Bus (IIC)
â Compatible with I2C Bus standard
â Multi-master operation
â Software programmable for one of 256 different serial clock frequencies
⢠112-Pin LQFP package
â I/O lines with 5V input and drive capability
â 5V A/D converter inputs
â Operation at 50MHz equivalent to 25MHz Bus Speed over -40ËC <= TA <= 125ËC
â Development support
â Single-wire background debug⢠mode (BDM)
â On-chip hardware breakpoints
1.3 Modes of Operation
User modes
⢠Normal and Emulation Operating Modes
â Normal Single-Chip Mode
â Normal Expanded Wide Mode
â Normal Expanded Narrow Mode
â Emulation Expanded Wide Mode
â Emulation Expanded Narrow Mode
⢠Special Operating Modes
â Special Single-Chip Mode with active Background Debug Mode
â Special Test Mode (Freescale use only)
â Special Peripheral Mode (Freescale use only)
Low power modes
⢠Stop Mode
⢠Pseudo Stop Mode
⢠Wait Mode
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