MC9328MX21S Datasheet, PDF (9/88 Pages) Freescale Semiconductor, Inc – MX family of microprocessors

Signal Descriptions
Table 2. i.MX21S Signal Descriptions (Continued)
Signal Name
PC_POE
PC_RW
PC_PWRON
CSPI1_MOSI
CSPI1_MISO
CSPI1_SS[2:0]
CSPI1_SCLK
CSPI1_RDY
CSPI2_MOSI
CSPI2_MISO
CSPI2_SS[2:0]
CSPI2_SCLK
TIN
TOUT1
(or simply TOUT)
TOUT2
TOUT3
USB_BYP
USB_PWR
USB_OC
USBG_RXDP
USBG_RXDM
USBG_TXDP
USBG_TXDM
USBG_RXDAT
USBG_OE
USBG_ON
USBG_FS
Function/Notes
PCMCIA Output Enable signal to enable voltage translation buffers and transceivers. This signal is
multiplexed with NFCLE signal of NF.
PCMCIA Read Write output signal to control external transceiver direction. Asserted high for read
access and negated low for write access. This signal is multiplexed with NFRE signal of NF.
PCMCIA input signal to indicate that the card power has been applied and stabilized.
CSPI
Master Out/Slave In signal
Master In/Slave Out signal
Slave Select (Selectable polarity) signal. CSPI1_SS2 is also multiplexed with USBG_RXDAT and
CSPI1_SS1 is multiplexed with EXT_DMAGRANT.
Serial Clock signal
Serial Data Ready signal. Also multiplexed with EXT_DMAREQ.
Master Out/Slave In signal. This signal is multiplexed with USBH2_TXDP signal of USB OTG.
Master In/Slave Out signal. This signal is multiplexed with USBH2_TXDM signal of USB OTG.
Slave Select (Selectable polarity) signals. These signals are multiplexed with USBH2_FS,
USBH2_RXDP and USBH2_RXDM signal of USB OTG
Serial Clock signal. This signal is multiplexed with USBH2_OE signal of USB OTG
General Purpose Timers
Timer Input Capture or Timer Input Clock—The signal on this input is applied to all 3 timers
simultaneously. This signal is muxed with the Walk-up Guard Mode WKGD signal in the PLL, Clock, and
Reset Controller module.
Timer Output signal from General Purpose Timer1 (GPT1). This signal is multiplexed with SYS_CLK1
and SYS_CLK2 signal of SSI1 and SSI2. The pin name of this signal is simply TOUT.
Timer Output signal from General Purpose Timer1 (GPT2). This signal is multiplexed with PWMO.
Timer Output signal from General Purpose Timer1 (GPT3). This signal is multiplexed with PWMO.
USB On-The-Go
USB Bypass input active low signal. This signal can only be used for USB function, not for GPIO.
USB Power output signal
USB Over current input signal. This signal can only be used for USB function, not for GPIO.
USB OTG Receive Data Plus input signal. This signal is muxed with SLCDC1_DAT15.
USB OTG Receive Data Minus input signal. This signal is muxed with SLCDC1_DAT14.
USB OTG Transmit Data Plus output signal. This signal is muxed with SLCDC1_DAT13.
USB OTG Transmit Data Minus output signal. This signal is muxed with SLCDC1_DAT12.
USB OTG Transceiver differential data receive signal. Multiplexed with CSPI1_SS2.
USB OTG Output Enable signal. This signal is muxed with SLCDC1_DAT11.
USB OTG Transceiver ON output signal. This signal is muxed with SLCDC1_DAT9.
USB OTG Full Speed output signal. This signal is multiplexed with external transceiver USBG_TXR_INT
signal of USB OTG. This signal is muxed with SLCDC1_DAT10.
MC9328MX21S Technical Data, Rev. 1.1
Freescale Semiconductor
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