MC9328MX21S Datasheet, PDF (46/88 Pages) Freescale Semiconductor, Inc – MX family of microprocessors

Specifications
Table 30. SSI to SSI1 Ports Timing Parameters (Continued)
Ref
No.
Parameter
1.8 V ± 0.1 V
3.0 V ± 0.3 V
Unit
Minimum Maximum Minimum Maximum
20 (Tx) CK high to FS (bl) low
10.22
17.63
8.82
16.24
ns
21 (Rx) CK high to FS (bl) low
10.79
19.67
9.39
18.28
ns
22 (Tx) CK high to FS (wl) high
10.22
17.63
8.82
16.24
ns
23 (Rx) CK high to FS (wl) high
10.79
19.67
9.39
18.28
ns
24 (Tx) CK high to FS (wl) low
10.22
17.63
8.82
16.24
ns
25 (Rx) CK high to FS (wl) low
10.79
19.67
9.39
18.28
ns
26 (Tx) CK high to STXD valid from high impedance
10.05
15.75
8.66
14.36
ns
27a (Tx) CK high to STXD high
10.00
15.63
8.61
14.24
ns
27b (Tx) CK high to STXD low
10.00
15.63
8.61
14.24
ns
28 (Tx) CK high to STXD high impedance
10.05
15.75
8.66
14.36
ns
29 SRXD setup time before (Rx) CK low
0.78
–
0.47
–
ns
30 SRXD hole time after (Rx) CK low
0
–
0
–
ns
Synchronous Internal Clock Operation (SSI1 Ports)
31 SRXD setup before (Tx) CK falling
32 SRXD hold after (Tx) CK falling
19.90
–
19.90
–
ns
0
–
0
–
ns
Synchronous External Clock Operation (SSI1 Ports)
33 SRXD setup before (Tx) CK falling
34 SRXD hold after (Tx) CK falling
2.59
–
2.28
–
ns
0
–
0
–
ns
1. All the timings for the SSI are given for a non-inverted serial clock polarity (TSCKP/RSCKP = 0) and a non-inverted frame sync
(TFSI/RFSI = 0). If the polarity of the clock and/or the frame sync have been inverted, all the timing remains valid by inverting
the clock signal STCK/SRCK and/or the frame sync STFS/SRFS shown in the tables and in the figures.
Table 31. SSI to SSI2 Ports Timing Parameters
Ref
No.
Parameter
1.8 V ± 0.1 V
3.0 V ± 0.3 V
Unit
Minimum Maximum Minimum Maximum
1 (Tx/Rx) CK clock period¹
2 (Tx) CK high to FS (bl) high
Internal Clock Operation¹ (SSI2 Ports)
90.91
–
0.01
0.15
90.91
0.01
–
ns
0.15
ns
3 (Rx) CK high to FS (bl) high
-0.21
0.05
-0.21
0.05
ns
4 (Tx) CK high to FS (bl) low
5 (Rx) CK high to FS (bl) low
0.01
0.15
0.01
0.15
ns
-0.21
0.05
-0.21
0.05
ns
6 (Tx) CK high to FS (wl) high
0.01
0.15
0.01
0.15
ns
7 (Rx) CK high to FS (wl) high
8 (Tx) CK high to FS (wl) low
-0.21
0.05
-0.21
0.05
ns
0.01
0.15
0.01
0.15
ns
9 (Rx) CK high to FS (wl) low
-0.21
0.05
-0.21
0.05
ns
10 (Tx) CK high to STXD valid from high impedance
0.34
0.72
0.34
0.72
ns
MC9328MX21S Technical Data, Rev. 1.1
46
Freescale Semiconductor