MC9328MX21S Datasheet, PDF (6/88 Pages) Freescale Semiconductor, Inc – MX family of microprocessors

Signal Descriptions
Table 2. i.MX21S Signal Descriptions (Continued)
Signal Name
Function/Notes
CAS
SDWE
SDCKE0
SDCKE1
SDCLK
SDRAM Column Address Select signal
SDRAM Write Enable signal
SDRAM Clock Enable 0
SDRAM Clock Enable 1
SDRAM Clock
Clocks and Resets
EXTAL26M
XTAL26M
EXTAL32K
XTAL32K
CLKO
EXT_48M
EXT_266M
RESET_IN
RESET_OUT
POR
CLKMODE[1:0]
OSC26M_TEST
TEST_WB[2:0]
TEST_WB[4:3]
WKGD
Crystal input (26MHz), or a 16 MHz to 32 MHz oscillator (or square-wave) input when the internal
oscillator circuit is shut down. When using an external signal source, feed this input with a square wave
signal switching from GND to VDDA.
Oscillator output to external crystal. When using an external signal source, float this output.
32 kHz or 32.768 kHz crystal input. When using an external signal source, feed this input with a square
wave signal switching from GND to QVDD5.
Oscillator output to external crystal. When using an external signal source, float this output.
Clock Out signal selected from internal clock signals. Please refer to clock controller for internal clock
selection.
This is a special factory test signal. To ensure proper operation, connect this signal to ground.
This is a special factory test signal. To ensure proper operation, connect this signal to ground.
Master Reset—External active low Schmitt trigger input signal. When this signal goes active, all modules
(except the reset module, SDRAMC module, and the clock control module) are reset.
Reset Out—Internal active low output signal from the Watchdog Timer module and is asserted from the
following sources: Power-on reset, External reset (RESET_IN), and Watchdog time-out.
Power On Reset—Active low Schmitt trigger input signal. The POR signal is normally generated by an
external RC circuit designed to detect a power-up event.
These are special factory test signals. To ensure proper operation, leave these signals as no connects.
This is a special factory test signal. To ensure proper operation, leave this signal as a no connect.
These are special factory test signals. However, these signals are also multiplexed with GPIO PORT E
as well as alternate keypad signals. If not using these signals for GPIO functions or for other multiplexed
functions, then configure as GPIO input with pull-up enabled, and leave as a no connect.
These are special factory test signals. To ensure proper operation, leave these signals as no connects.
Battery indicator input used to qualify the walk-up process. Also multiplexed with TIN.
JTAG
For termination recommendations, see the Table “JTAG pinouts” in the Multi-ICE^® User Guide from ARM^® Limited.
TRST
TDO
TDI
TCK
TMS
JTAG_CTRL
Test Reset Pin—External active low signal used to asynchronously initialize the JTAG controller.
Serial Output for test instructions and data. Changes on the falling edge of TCK.
Serial Input for test instructions and data. Sampled on the rising edge of TCK.
Test Clock to synchronize test logic and control register access through the JTAG port.
Test Mode Select to sequence the JTAG test controller’s state machine. Sampled on the rising edge of
TCK.
JTAG Controller select signal—JTAG_CTRL is sampled during the rising edge of TRST. Must be pulled
to logic high for proper JTAG interface to debugger. Pulling JTAG_CRTL low is for internal test purposes
only.
MC9328MX21S Technical Data, Rev. 1.1
6
Freescale Semiconductor