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MC9328MX21S Datasheet, PDF (40/88 Pages) Freescale Semiconductor, Inc – MX family of microprocessors | |||
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Specifications
Table 27. SDRAM Write Cycle Timing Parameter
Ref
No.
Parameter
1.8 V ± 0.1 V
3.0 V ± 0.3 V
Unit
Minimum Maximum Minimum Maximum
1 SDRAM clock high-level width
3.00
â
3
â
ns
2 SDRAM clock low-level width
3.00
â
3
â
ns
3 SDRAM clock cycle time
7.5
â
7.5
â
ns
4 Address setup time
3.67
â
2
â
ns
5 Address hold time
2.95
â
2
â
ns
6 Precharge cycle period1
tRP2
â
tRP2
â
ns
7 Active to read/write command delay
tRCD2
â
tRCD2
â
ns
8 Data setup time
3.41
â
2
â
ns
9 Data hold time
2.45
â
2
â
ns
1. Precharge cycle timing is included in the write timing diagram.
2. tRP and tRCD = SDRAM clock cycle time. These settings can be found in the i.MX21 reference manual.
SDCLK
CS
13
2
RAS
6
CAS
WE
4
5
ADDR
BA
DQ
7
7
ROW/BA
DQM
40
Figure 32. SDRAM Refresh Timing Diagram
MC9328MX21S Technical Data, Rev. 1.1
Freescale Semiconductor
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