MC9328MX21S Datasheet, PDF (16/88 Pages) Freescale Semiconductor, Inc – MX family of microprocessors

Specifications
3.5 DPLL Timing Specifications
Parameters of the DPLL are given in Table 11. In this table, T_ref is a reference clock period after the
predivider and T_dck is the output double clock period.
Table 11. DPLL Specifications
Parameter
Reference clock frequency range
Pre-divider output clock frequency
range
Double clock frequency range
Pre-divider factor (PD)
Total multiplication factor (MF)
MF integer part
MF numerator
MF denominator
Frequency lock-in time after
full reset
Frequency lock-in time after
partial reset
Phase lock-in time after
full reset
Phase lock-in time after
partial reset
Frequency jitter (p-p)
Phase jitter (p-p)
Power dissipation
Test Conditions
Vcc = 1.5V
Vcc = 1.5V
Vcc = 1.5V
–
Includes both integer and fractional parts
–
Should be less than the denominator
–
FOL mode for non-integer MF
(does not include pre-multi lock-in time)
FOL mode for non-integer MF
(does not include pre-multi lock-in time)
FPL mode and integer MF
(does not include pre-multi lock-in time)
FPL mode and integer MF
(does not include pre-multi lock-in time)
–
Integer MF, FPL mode, Vcc=1.7V
FOL mode, integer MF,
f_dck = 560 MHz, Vcc = 1.5V
Minimum
16
16
220
1
5
5
0
1
350
220
480
360
–
–
–
Typical
–
–
–
–
–
–
–
–
400
280
530
410
0.02
1.0
1.5
Maximum
320
32
560
16
15
15
1022
1023
450
330
580
460
0.03
1.5
–
Unit
MHz
MHz
MHz
–
–
–
–
–
T_ref
T_ref
T_ref
T_ref
2•T_dck
ns
mW
(Avg)
MC9328MX21S Technical Data, Rev. 1.1
16
Freescale Semiconductor