MC9328MX21S Datasheet, PDF (48/88 Pages) Freescale Semiconductor, Inc – MX family of microprocessors

Specifications
Table 32. SSI to SSI3 Ports Timing Parameters
Ref
No.
Parameter
1.8 V ± 0.1 V
3.0 V ± 0.3 V
Unit
Minimum Maximum Minimum Maximum
Internal Clock Operation¹ (SSI3 Ports)
1 (Tx/Rx) CK clock period¹
90.91
–
2 (Tx) CK high to FS (bl) high
-2.09
-0.66
3 (Rx) CK high to FS (bl) high
-2.74
-0.84
4 (Tx) CK high to FS (bl) low
-2.09
-0.66
5 (Rx) CK high to FS (bl) low
-2.74
-0.84
6 (Tx) CK high to FS (wl) high
-2.09
-0.66
7 (Rx) CK high to FS (wl) high
-2.74
-0.84
8 (Tx) CK high to FS (wl) low
-2.09
-0.66
9 (Rx) CK high to FS (wl) low
-2.74
-0.84
10 (Tx) CK high to STXD valid from high impedance
-1.73
-0.26
11a (Tx) CK high to STXD high
-2.87
-0.80
11b (Tx) CK high to STXD low
-2.87
-0.80
12 (Tx) CK high to STXD high impedance
-1.73
-0.26
13 SRXD setup time before (Rx) CK low
22.77
–
14 SRXD hold time after (Rx) CK low
0
–
90.91
-2.09
-2.74
-2.09
-2.74
-2.09
-2.74
-2.09
-2.74
-1.73
-2.87
-2.87
-1.73
22.77
0
–
ns
-0.66
ns
-0.84
ns
-0.66
ns
-0.84
ns
-0.66
ns
-0.84
ns
-0.66
ns
-0.84
ns
-0.26
ns
-0.80
ns
-0.80
ns
-0.26
ns
–
ns
–
ns
External Clock Operation (SSI3 Ports)
15 (Tx/Rx) CK clock period¹
90.91
–
16 (Tx/Rx) CK clock high period
36.36
–
17 (Tx/Rx) CK clock low period
36.36
–
18 (Tx) CK high to FS (bl) high
9.62
17.10
19 (Rx) CK high to FS (bl) high
10.30
19.54
20 (Tx) CK high to FS (bl) low
9.62
17.10
21 (Rx) CK high to FS (bl) low
10.30
19.54
22 (Tx) CK high to FS (wl) high
9.62
17.10
23 (Rx) CK high to FS (wl) high
10.30
19.54
24 (Tx) CK high to FS (wl) low
9.62
17.10
25 (Rx) CK high to FS (wl) low
10.30
19.54
26 (Tx) CK high to STXD valid from high impedance
9.02
16.46
27a (Tx) CK high to STXD high
8.48
15.32
27b (Tx) CK high to STXD low
8.48
15.32
90.91
36.36
36.36
7.90
8.58
7.90
8.58
7.90
8.58
7.90
8.58
7.29
6.75
6.75
–
ns
–
ns
–
ns
15.61
ns
18.05
ns
15.61
ns
18.05
ns
15.61
ns
18.05
ns
15.61
ns
18.05
ns
14.97
ns
13.83
ns
13.83
ns
MC9328MX21S Technical Data, Rev. 1.1
48
Freescale Semiconductor