MC9328MX21S Datasheet, PDF (29/88 Pages) Freescale Semiconductor, Inc – MX family of microprocessors

Host Command
N_CR cycles
CMD S T Content CRC E Z Z P ****** P S T
Response
Content CRC E Z Z Z
Command response timing (data transfer mode)
CMD S T
Response
N_RC cycles
Host Command
Content CRC E Z
******
Z S T Content CRC E Z Z Z
Timing response end to next CMD start (data transfer mode)
Specifications
Host Command
N_CC cycles
Host Command
CMD S T Content CRC E Z
******
Z S T Content CRC E Z Z Z
Timing of command sequences (all modes)
Figure 19. Timing Diagrams at Data Transfer Mode
Figure 20 shows basic read operation timing. In a read operation, the sequence starts with a single block
read command (which specifies the start address in the argument field). The response is sent on the
SD_CMD lines as usual. Data transmission from the card starts after the access time delay N_AC, beginning
from the last bit of the read command. If the system is in multiple block read mode, the card sends a
continuous flow of data blocks with distance N_AC until the card sees a stop transmission command. The
data stops two clock cycles after the end bit of the stop command.
MC9328MX21S Technical Data, Rev. 1.1
Freescale Semiconductor
29