MC9328MX21S Datasheet, PDF (19/88 Pages) Freescale Semiconductor, Inc – MX family of microprocessors

Ext_DMAReq
Specifications
Ext_DMAGrant
t_{min_assert}
Figure 4. Assertion of DMA External Grant Signal
Figure 5 shows the safe maximum time for which External DMA request can be kept asserted, after
sensing grant signal active such that a new burst is not initiated.
Ext_DMAReq
Ext_DMAGrant
t_{max_req_assert}
Data read from
External device
t_{max_read}
Data written to
External device
t_{max_write}
NOTE: Assuming in worst case the data is read/written from/to External device as per the above waveform.
Figure 5. Safe Maximum Timings for External Request De-Assertion
Table 13. DMA External Request and Grant Timing Parameters
Parameter
Description
3.0 V
WCS
BCS
1.8 V
Unit
WCS
BCS
t_{min_assert} Minimum assertion time of External Grant 8 hclk + 8.6 8 hclk + 2.74 8 hclk + 7.17 8 hclk + 3.25 ns
signal
t_{max_req_assert} Maximum External request assertion time 9 hclk - 20.66 9 hclk - 6.7 9 hclk - 17.96 9 hclk - 8.16 ns
after assertion of Grant signal
t_{max_read} Maximum External request assertion time 8 hclk - 6.21 8 hclk - 0.77 8 hclk - 5.84 8 hclk - 0.66 ns
after first read completion
t_{max_write} Maximum External request assertion time 3 hclk - 15.87 3 hclk - 8.83 3 hclk - 15.9 3 hclk - 9.12 ns
after completion of first write
3.8 CSPI Timing Diagrams
To use the internal transmit (TX) and receive (RX) data FIFOs when the CSPI1 module is configured as a
master, two control signals are used for data transfer rate control: the SS signal (output) and the SPI_RDY
signal (input). The SPI 1 Sample Period Control Register (PERIODREG1) and the SPI 2 Sample Period
Control Register (PERIODREG2) can also be programmed to a fixed data transfer rate for either CSPI1
or CSPI2. When the CSPI1 module is configured as a slave, the user can configure the SPI 1 Control
Register (CONTROLREG1) to match the external CSPI master’s timing. In this configuration, SS
MC9328MX21S Technical Data, Rev. 1.1
Freescale Semiconductor
19