MC9328MX21S Datasheet, PDF (51/88 Pages) Freescale Semiconductor, Inc – MX family of microprocessors

Specifications
Set WR1/RD
Auto Clear WR1/RD Set WR1/RD
Auto Clear WR1/R
Read Timing
Read “0” Slot 117us
60us
Read “1” Slot 117us
one-wire
BUS
5us
13us
One-Wire samples
(set RDST)
5us
13us
Figure 41. Read Timing
One-Wire samples
(set RDST)
The precision of the generated clock is very important to get a proper behavior of the one-wire module.
This module is based on a state machine which undertakes actions at defined times.
Table 33. System Timing Requirements
Times
RSTL
PST
RSTH
LOW0
LOWR
READ_sample
Values
(Microsec)
511
68
512
100
5
13
Minimum
(Microsec)
480
60
480
60
1
–
Maximum
(microsec)
–
75
–
120
15
15
Absolute
Precision
31
7
32
20
4
2
Relative
Precision
0.0645
0.1
0.0645
0.2
0.8
0.15
The most stringent constraint is 0.0645 as a relative time imprecision.
The time relative precision is directly derived from the frequency of the derivative clock (f):
Time relative precision = 1/f -1 = divider/clock (MHz) - 1
The Figure 34 gathers relative time precision for different main clock frequencies.
Table 34. System Clock Requirements
Main Clock Frequency (MHz)
13
16.8
19.44
Clock divide ratio
Generated frequency (MHz)
Relative time imprecision
13
17
19
1
0.9882
1.023
0
0.0117
0.023
This shows that the user should take care of the main clock frequency when using the one-wire module. If
the main clock is an exact integer multiple of 1 MHz, then the generated frequency will be exactly 1 MHz.
NOTE:
A main clock frequency below 10 MHz might cause a misbehavior of the module.
MC9328MX21S Technical Data, Rev. 1.1
Freescale Semiconductor
51