MC9328MX21S Datasheet, PDF (2/88 Pages) Freescale Semiconductor, Inc – MX family of microprocessors

Introduction
devices to be used as primary or secondary non-volatile storage. The on-chip error correction code (ECC)
and parity checking circuitry of the NAND Flash controller frees the CPU for other tasks. WLAN,
Bluetooth and expansion options are provided through PCMCIA/CF, USB, and MMC/SD host controllers.
The device is packaged in a 289-pin MAPBGA.
System Control
JTAG/Multi- ICE^®
System Boot
Clock Management
Standard System I/O
Timers x 3
PWM
WDOG
RTC
GPIO
DMAC
i.MX21S
ARM9 Platform
ARM926EJ-S
MAX
I Cache
MMU
D Cache
Bus Control
Internal Control Memory Control
Connectivity
CSPI x 2
SSI x 2
I²C
Audio Mux
UART 1, 3, & 4
1-Wire
FIRI
USB OTG/ 1 Host
Human Interface
LCD Controller
SLCD Controller
Keypad
Memory Interface
SDRAMC
WEIM
NFC
Memory Expansion
MMC/SD x 2
PCMCIA/CF
Figure 1. i.MX21S Functional Block Diagram
1.1 Conventions
This document uses the following conventions:
• OVERBAR is used to indicate a signal that is active when pulled low: for example, RESET.
• Logic level one is a voltage that corresponds to Boolean true (1) state.
• Logic level zero is a voltage that corresponds to Boolean false (0) state.
• To set a bit or bits means to establish logic level one.
• To clear a bit or bits means to establish logic level zero.
• A signal is an electronic construct whose state conveys or changes in state convey information.
• A pin is an external physical connection. The same pin can be used to connect a number of signals.
• Asserted means that a discrete signal is in active logic state.
— Active low signals change from logic level one to logic level zero.
— Active high signals change from logic level zero to logic level one.
• Negated means that an asserted discrete signal changes logic state.
— Active low signals change from logic level zero to logic level one.
— Active high signals change from logic level one to logic level zero.
MC9328MX21S Technical Data, Rev. 1.1
2
Freescale Semiconductor