MC68HC908GZ60 Datasheet, PDF (86/352 Pages) Freescale Semiconductor, Inc – Microcontrollers

Clock Generator Module (CGM)
4.5.3 PLL Multiplier Select Register High
The PLL multiplier select register high (PMSH) contains the programming information for the high byte of
the modulo feedback divider.
Address:
Read:
Write:
Reset:
$0038
Bit 7
6
5
4
3
2
1
0
0
0
0
MUL11 MUL10 MUL9
0
0
0
0
0
0
0
= Unimplemented
Figure 4-6. PLL Multiplier Select Register High (PMSH)
Bit 0
MUL8
0
MUL11–MUL8 — Multiplier Select Bits
These read/write bits control the high byte of the modulo feedback divider that selects the VCO
frequency multiplier N. (See 4.3.3 PLL Circuits and 4.3.6 Programming the PLL.) A value of $0000 in
the multiplier select registers configures the modulo feedback divider the same as a value of $0001.
Reset initializes the registers to $0040 for a default multiply value of 64.
NOTE
The multiplier select bits have built-in protection such that they cannot be
written when the PLL is on (PLLON = 1).
PMSH[7:4] — Unimplemented Bits
These bits have no function and always read as 0s.
4.5.4 PLL Multiplier Select Register Low
The PLL multiplier select register low (PMSL) contains the programming information for the low byte of
the modulo feedback divider.
Address:
Read:
Write:
Reset:
$0038
Bit 7
6
5
4
3
2
1
MUL7
MUL6
MUL5
MUL4
MUL3
MUL2
MUL1
0
1
0
0
0
0
0
Figure 4-7. PLL Multiplier Select Register Low (PMSL)
Bit 0
MUL0
0
NOTE
For applications using 1–8 MHz reference frequencies this register must be
reprogrammed before enabling the PLL. The reset value of this register will
cause applications using 1–8 MHz reference frequencies to become
unstable if the PLL is enabled without programming an appropriate value.
The programmed value must not allow the VCO clock to exceed 32 MHz.
See 4.3.6 Programming the PLL for detailed instructions on choosing the
proper value for PMSL.
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
86
Freescale Semiconductor