MC68HC908GZ60 Datasheet, PDF (292/352 Pages) Freescale Semiconductor, Inc – Microcontrollers

Timer Interface Module (TIM2)
NOTE
Setting the TSTOP and TRST bits simultaneously stops the TIM2 counter
at a value of $0000.
PS[2:0] — Prescaler Select Bits
These read/write bits select either the T2CH0 pin or one of the seven prescaler outputs as the input to
the TIM2 counter as Table 19-1 shows. Reset clears the PS[2:0] bits.
Table 19-1. Prescaler Selection
PS[2:0]
000
001
010
011
100
101
110
111
TIM2 Clock Source
Internal bus clock ÷1
Internal bus clock ÷ 2
Internal bus clock ÷ 4
Internal bus clock ÷ 8
Internal bus clock ÷ 16
Internal bus clock ÷ 32
Internal bus clock ÷ 64
T2CH0
19.8.2 TIM2 Counter Registers
The two read-only TIM2 counter registers contain the high and low bytes of the value in the TIM2 counter.
Reading the high byte (T2CNTH) latches the contents of the low byte (T2CNTL) into a buffer. Subsequent
reads of T2CNTH do not affect the latched T2CNTL value until T2CNTL is read. Reset clears the TIM2
counter registers. Setting the TIM2 reset bit (TRST) also clears the TIM2 counter registers.
NOTE
If T2CNTH is read during a break interrupt, be sure to unlatch T2CNTL by
reading T2CNTL before exiting the break interrupt. Otherwise, T2CNTL
retains the value latched during the break.
Address: $002C T2CNTH
Bit 7
6
5
4
3
2
1
Bit 0
Read: BIT 15 BIT 14 BIT 13 BIT 12 BIT 11 BIT 10
BIT 9
BIT 8
Write:
Reset: 0
0
0
0
0
0
0
0
Address: $002D T2CNTL
Bit 7
6
5
4
3
2
1
Bit 0
Read: BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Write:
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 19-6. TIM2 Counter Registers (T2CNTH and T2CNTL)
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
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Freescale Semiconductor