MC68HC908GZ60 Datasheet, PDF (231/352 Pages) Freescale Semiconductor, Inc – Microcontrollers

CLI
LDA #$FF
INT1
PSHH
PULH
RTI
Exception Control
BACKGROUND
ROUTINE
INT1 INTERRUPT SERVICE ROUTINE
INT2
PSHH
INT2 INTERRUPT SERVICE ROUTINE
PULH
RTI
Figure 15-11. Interrupt Recognition Example
15.5.1.2 SWI Instruction
The SWI instruction is a non-maskable instruction that causes an interrupt regardless of the state of the
interrupt mask (I bit) in the condition code register.
NOTE
A software interrupt pushes PC onto the stack. A software interrupt does
not push PC – 1, as a hardware interrupt does.
15.5.1.3 Interrupt Status Registers
The flags in the interrupt status registers identify maskable interrupt sources. Table 15-3 summarizes the
interrupt sources, hardware flag bits, hardware interrupt mask bits, interrupt status register flags, interrupt
priority, and exception vectors. The interrupt status registers can be useful for debugging.
Interrupt Status Register 1
Address: $FE04
Bit 7
6
5
4
3
2
1
Bit 0
Read: IF6
IF5
IF4
IF3
IF2
IF1
0
0
Write: R
R
R
R
R
R
R
R
Reset: 0
0
0
0
0
0
0
0
R
= Reserved
Figure 15-12. Interrupt Status Register 1 (INT1)
IF6–IF1 — Interrupt Flags 1–6
These flags indicate the presence of interrupt requests from the sources shown in Table 15-3.
1 = Interrupt request present
0 = No interrupt request present
Bit 0 and Bit 1 — Always read 0
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
Freescale Semiconductor
231