MC68HC908GZ60 Datasheet, PDF (164/352 Pages) Freescale Semiconductor, Inc – Microcontrollers

MSCAN08 Controller (MSCAN08)
12.13.8 MSCAN08 Transmitter Control Register
Address:
Read:
Write:
Reset:
$0507
Bit 7
6
5
4
3
0
0
ABTRQ2 ABTRQ1 ABTRQ0
2
TXEIE2
1
TXEIE1
0
0
0
0
0
0
0
= Unimplemented
Figure 12-23. Transmitter Control Register (CTCR)
Bit 0
TXEIE0
0
ABTRQ2–ABTRQ0 — Abort Request
The CPU sets an ABTRQx bit to request that an already scheduled message buffer (TXE = 0) be
aborted. The MSCAN08 will grant the request if the message has not already started transmission, or
if the transmission is not successful (lost arbitration or error). When a message is aborted the
associated TXE and the abort acknowledge flag (ABTAK) (see 12.13.7 MSCAN08 Transmitter Flag
Register) will be set and an TXE interrupt is generated if enabled. The CPU cannot reset ABTRQx.
ABTRQx is cleared implicitly whenever the associated TXE flag is set.
1 = Abort request pending
0 = No abort request
NOTE
The software must not clear one or more of the TXE flags in CTFLG and
simultaneously set the respective ABTRQ bit(s).
TXEIE2–TXEIE0 — Transmitter Empty Interrupt Enable
1 = A transmitter empty (transmit buffer available for transmission) event results in a transmitter
empty interrupt.
0 = No interrupt is generated from this event.
NOTE
The CTCR register is held in the reset state when the SFTRES bit in
CMCR0 is set.
12.13.9 MSCAN08 Identifier Acceptance Control Register
Address: $0508
Bit 7
6
5
4
3
2
1
Bit 0
Read: 0
0
IDHIT2 IDHIT1 IDHIT0
IDAM2 IDAM1 IDAM0
Write:
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 12-24. Identifier Acceptance Control Register (CIDAC)
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
164
Freescale Semiconductor