MC68HC908GZ60 Datasheet, PDF (225/352 Pages) Freescale Semiconductor, Inc – Microcontrollers

Reset and System Initialization
15.3 Reset and System Initialization
The MCU has these reset sources:
• Power-on reset module (POR)
• External reset pin (RST)
• Computer operating properly module (COP)
• Low-voltage inhibit module (LVI)
• Illegal opcode
• Illegal address
• Forced monitor mode entry reset (MODRST)
All of these resets produce the vector $FFFE:$FFFF ($FEFE:$FEFF in monitor mode) and assert the
internal reset signal (IRST). IRST causes all registers to be returned to their default values and all
modules to be returned to their reset states.
An internal reset clears the SIM counter (see 15.4 SIM Counter), but an external reset does not. Each of
the resets sets a corresponding bit in the SIM reset status register (SRSR). See 15.7 SIM Registers.
A reset immediately stops the operation of the instruction being executed. Reset initializes certain control
and status bits. Reset selects CGMXCLK divided by four as the bus clock.
15.3.1 External Pin Reset
The RST pin circuit includes an internal pullup device. Pulling the asynchronous RST pin low halts all
processing. The PIN bit of the SIM reset status register (SRSR) is set as long as RST is held low for at
least the minimum t_RL time and no other reset sources are present. Figure 15-4 shows the relative timing.
CGMOUT
RST
IAB
PC
VECT H VECT L
Figure 15-4. External Reset Timing
15.3.2 Active Resets from Internal Sources
All internal reset sources actively pull the RST pin low for 32 CGMXCLK cycles to allow resetting of
external peripherals. The internal reset continues to be asserted for an additional 32 cycles at which point
the reset vector will be fetched. See Figure 15-5. An internal reset can be caused by an illegal address,
illegal opcode, COP timeout, LVI, or POR. See Figure 15-6.
NOTE
For LVI or POR resets, the SIM cycles through 4096 CGMXCLK cycles
during which the SIM forces the RST pin low. The internal reset signal then
follows the sequence from the falling edge of RST shown in Figure 15-5.
The COP reset is asynchronous to the bus clock.
The active reset feature allows the part to issue a reset to peripherals and other chips within a system
built around the MCU.
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
Freescale Semiconductor
225