MC68HC908GZ60 Datasheet, PDF (158/352 Pages) Freescale Semiconductor, Inc – Microcontrollers

MSCAN08 Controller (MSCAN08)
CLKSRC — Clock Source
This flag defines which clock source the MSCAN08 module is driven from (see 12.10 Clock System).
1 = The MSCAN08 clock source is CGMOUT (see Figure 12-8).
0 = The MSCAN08 clock source is CGMXCLK/2 (see Figure 12-8).
NOTE
The CMCR1 register can be written only if the SFTRES bit in the MSCAN08
module control register is set
12.13.3 MSCAN08 Bus Timing Register 0
Address: $0502
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
SJW1
SJW0
BRP5
BRP4
BRP3
BRP2
BRP1
BRP0
Reset: 0
0
0
0
0
0
0
0
Figure 12-18. Bus Timing Register 0 (CBTR0)
SJW1 and SJW0 — Synchronization Jump Width
The synchronization jump width (SJW) defines the maximum number of time quanta (T_q) clock cycles
by which a bit may be shortened, or lengthened, to achieve resynchronization on data transitions on
the bus (see Table 12-6).
Table 12-6. Synchronization Jump Width
SJW1
0
0
1
1
SJW0
0
1
0
1
Synchronization
Jump Width
1 T_q cycle
2 T_q cycle
3 T_q cycle
4 T_q cycle
BRP5–BRP0 — Baud Rate Prescaler
These bits determine the time quanta (T_q) clock, which is used to build up the individual bit timing,
according to Table 12-7.
BRP5
0
0
0
0
:
:
1
Table 12-7. Baud Rate Prescaler
BRP4
0
0
0
0
:
:
1
BRP3
0
0
0
0
:
:
1
BRP2
0
0
0
0
:
:
1
BRP1
0
0
1
1
:
:
1
BRP0
0
1
0
1
:
:
1
Prescaler
Value (P)
1
2
3
4
:
:
64
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
158
Freescale Semiconductor