MC68HC908GZ60 Datasheet, PDF (249/352 Pages) Freescale Semiconductor, Inc – Microcontrollers

Error Conditions
In this case, an overflow can be missed easily. Since no more SPRF interrupts can be generated until this
OVRF is serviced, it is not obvious that bytes are being lost as more transmissions are completed. To
prevent this, either enable the OVRF interrupt or do another read of the SPSCR following the read of the
SPDR. This ensures that the OVRF was not set before the SPRF was cleared and that future
transmissions can set the SPRF bit. Figure 16-11 illustrates this process. Generally, to avoid this second
SPSCR read, enable the OVRF to the CPU by setting the ERRIE bit.
BYTE 1
SPI RECEIVE
1
COMPLETE
SPRF
BYTE 2
5
BYTE 3
7
BYTE 4
11
OVRF
READ
SPSCR
READ
SPDR
2
4
3
6
9
12
14
8
10
13
1 BYTE 1 SETS SPRF BIT.
2 CPU READS SPSCR WITH SPRF BIT SET
AND OVRF BIT CLEAR.
3 CPU READS BYTE 1 IN SPDR,
CLEARING SPRF BIT.
4 CPU READS SPSCR AGAIN
TO CHECK OVRF BIT.
5 BYTE 2 SETS SPRF BIT.
6 CPU READS SPSCR WITH SPRF BIT SET
AND OVRF BIT CLEAR.
7 BYTE 3 SETS OVRF BIT. BYTE 3 IS LOST.
8 CPU READS BYTE 2 IN SPDR,
CLEARING SPRF BIT.
9 CPU READS SPSCR AGAIN
TO CHECK OVRF BIT.
10 CPU READS BYTE 2 SPDR,
CLEARING OVRF BIT.
11 BYTE 4 SETS SPRF BIT.
12 CPU READS SPSCR.
13 CPU READS BYTE 4 IN SPDR,
CLEARING SPRF BIT.
14 CPU READS SPSCR AGAIN
TO CHECK OVRF BIT.
Figure 16-11. Clearing SPRF When OVRF Interrupt Is Not Enabled
16.6.2 Mode Fault Error
Setting SPMSTR selects master mode and configures the SPSCK and MOSI pins as outputs and the
MISO pin as an input. Clearing SPMSTR selects slave mode and configures the SPSCK and MOSI pins
as inputs and the MISO pin as an output. The mode fault bit, MODF, becomes set any time the state of
the slave select pin, SS, is inconsistent with the mode selected by SPMSTR.
To prevent SPI pin contention and damage to the MCU, a mode fault error occurs if:
• The SS pin of a slave SPI goes high during a transmission
• The SS pin of a master SPI goes low at any time
For the MODF flag to be set, the mode fault error enable bit (MODFEN) must be set. Clearing the
MODFEN bit does not clear the MODF flag but does prevent MODF from being set again after MODF is
cleared.
MODF generates a receiver/error CPU interrupt request if the error interrupt enable bit (ERRIE) is also
set. The SPRF, MODF, and OVRF interrupts share the same CPU interrupt vector. (See Figure 16-12.)
It is not possible to enable MODF or OVRF individually to generate a receiver/error CPU interrupt request.
However, leaving MODFEN low prevents MODF from being set.
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
Freescale Semiconductor
249