MC68HC908GZ60 Datasheet, PDF (290/352 Pages) Freescale Semiconductor, Inc – Microcontrollers

Timer Interface Module (TIM2)
19.6 TIM2 During Break Interrupts
A break interrupt stops the TIM2 counter and inhibits input captures.
The system integration module (SIM) controls whether status bits in other modules can be cleared during
the break state. The BCFE bit in the SIM break flag control register (SBFCR) enables software to clear
status bits during the break state. (See 15.7.3 Break Flag Control Register.)
To allow software to clear status bits during a break interrupt, write a 1 to the BCFE bit. If a status bit is
cleared during the break state, it remains cleared when the MCU exits the break state.
To protect status bits during the break state, write a 0 to the BCFE bit. With BCFE at 0 (its default state),
software can read and write I/O registers during the break state without affecting status bits. Some status
bits have a 2-step read/write clearing procedure. If software does the first step on such a bit before the
break, the bit cannot change during the break state as long as BCFE is at 0. After the break, doing the
second step clears the status bit.
19.7 I/O Signals
Port D shares two of its pins with the TIM2. Port F shares four of its pins with the TIM2. PTD6/T2CH0 is
an external clock input to the TIM2 prescaler. The six TIM2 channel I/O pins are PTD6/T2CH0,
PTD7/T2CH1, PTF4/T2CH2, PTF5/T2CH3, PTF6/T2CH4, and PTF7/T2CH5.
19.7.1 TIM2 Clock Pin (T2CH0)
T2CH0 is an external clock input that can be the clock source for the TIM2 counter instead of the
prescaled internal bus clock. Select the T2CH0 input by writing 1s to the three prescaler select bits,
PS[2:0]. (See 19.8.1 TIM2 Status and Control Register.) The minimum TCLK pulse width is specified in
21.14 Timer Interface Module Characteristics. The maximum TCLK frequency is the least: 4 MHz or bus
frequency ÷ 2.
When the PTD6/T2CH0 pin is the TIM2 clock input, it is an input regardless of the state of the DDRD6 bit
in data direction register D.
19.7.2 TIM2 Channel I/O Pins (T2CH5:T2CH2 and T2CH1:T2CH0)
Each channel I/O pin is programmable independently as an input capture pin or an output compare pin.
T2CH0, T2CH2, and T2CH4 can be configured as buffered output compare or buffered PWM pins.
19.8 I/O Registers
These I/O registers control and monitor TIM2 operation:
• TIM2 status and control register (T2SC)
• TIM2 counter registers (T2CNTH:T2CNTL)
• TIM2 counter modulo registers (T2MODH:T2MODL)
• TIM2 channel status and control registers (T2SC0, T2SC1, T2SC2, T2SC3, T2SC4, and T2SC5)
• TIM2 channel registers (T2CH0H:T2CH0L, T2CH1H:T2CH1L, T2CH2H:T2CH2L,
T2CH3H:T2CH3L, T2CH4H:T2CH4L, and T2CH5H:T2CH5L)
MC68HC908GZ60 • MC68HC908GZ48 • MC68HC908GZ32 Data Sheet, Rev. 6
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Freescale Semiconductor