S9S12G128F0MLL Datasheet, PDF (786/1292 Pages) Freescale Semiconductor, Inc – Reference Manual and Date Sheet

16 KByte Flash Module (S12FTMRG16K1V1)
Address
& Name
7
6
5
4
3
2
1
0
0x0011
R
0
0
0
0
0
0
0
0
FRSV5 _W
0x0012
R
0
0
0
0
0
0
0
0
FRSV6 _W
0x0013
R
0
0
0
0
0
0
0
0
FRSV7 _W
= Unimplemented or Reserved
Figure 24-4. FTMRG16K1 Register Summary (continued)
24.3.2.1 Flash Clock Divider Register (FCLKDIV)
The FCLKDIV register is used to control timed events in program and erase algorithms.
Offset Module Base + 0x0000
7
6
5
4
3
2
1
0
R FDIVLD
W
FDIVLCK
FDIV[5:0]
Reset
0
0
0
0
0
0
0
0
= Unimplemented or Reserved
Figure 24-5. Flash Clock Divider Register (FCLKDIV)
All bits in the FCLKDIV register are readable, bit 7 is not writable, bit 6 is write-once-hi and controls the
writability of the FDIV field in normal mode. In special mode, bits 6-0 are writable any number of times
but bit 7 remains unwritable.
CAUTION
The FCLKDIV register should never be written while a Flash command is
executing (CCIF=0).
Table 24-7. FCLKDIV Field Descriptions
Field
7
FDIVLD
Description
Clock Divider Loaded
0 FCLKDIV register has not been written since the last reset
1 FCLKDIV register has been written since the last reset
MC9S12G Family Reference Manual, Rev.1.23
788
Freescale Semiconductor