S9S12G128F0MLL Datasheet, PDF (471/1292 Pages) Freescale Semiconductor, Inc – Reference Manual and Date Sheet

13.2 Signal Description
This section lists all inputs to the ADC10B12C block.
Analog-to-Digital Converter (ADC10B12CV2)
13.2.1 Detailed Signal Descriptions
13.2.1.1 ANx (x = 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0)
This pin serves as the analog input Channel x. It can also be configured as digital port or external trigger
for the ATD conversion.
13.2.1.2 ETRIG3, ETRIG2, ETRIG1, ETRIG0
These inputs can be configured to serve as an external trigger for the ATD conversion.
Refer to device specification for availability and connectivity of these inputs!
13.2.1.3 VRH, VRL
VRH is the high reference voltage, VRL is the low reference voltage for ATD conversion.
13.2.1.4 VDDA, VSSA
These pins are the power supplies for the analog circuitry of the ADC10B12C block.
13.3 Memory Map and Register Definition
This section provides a detailed description of all registers accessible in the ADC10B12C.
13.3.1 Module Memory Map
Figure 13-2 gives an overview on all ADC10B12C registers.
NOTE
Register Address = Base Address + Address Offset, where the Base Address
is defined at the MCU level and the Address Offset is defined at the module
level.
Address
0x0000
0x0001
0x0002
Name
ATDCTL0
ATDCTL1
ATDCTL2
Bit 7
R
Reserved
W
R _ETRIGSEL
W
R
0
W
6
0
SRES1
AFFC
5
4
3
2
1
Bit 0
0
0
WRAP3 WRAP2 WRAP1 WRAP0
SRES0 SMP_DIS ETRIGCH3 ETRIGCH2 ETRIGCH1 ETRIGCH0
Reserved ETRIGLE ETRIGP ETRIGE ASCIE ACMPIE
= Unimplemented or Reserved
Figure 13-2. ADC10B12C Register Summary (Sheet 1 of 3)
MC9S12G Family Reference Manual, Rev.1.23
Freescale Semiconductor
473