S9S12G128F0MLL Datasheet, PDF (314/1292 Pages) Freescale Semiconductor, Inc – Reference Manual and Date Sheet

S12S Debug Module (S12SDBGV2)
8.2 External Signal Description
There are no external signals associated with this module.
8.3 Memory Map and Registers
8.3.1 Module Memory Map
A summary of the registers associated with the DBG sub-block is shown in Figure 8-2. Detailed
descriptions of the registers and bits are given in the subsections that follow.
Address
0x0020
0x0021
Name
R
DBGC1
W
R
DBGSR
W
Bit 7
ARM
1_TBF
R
0
0x0022 DBGTCR
W
R
0
0x0023 DBGC2
W
R Bit 15
0x0024 DBGTBH
W
0x0025
0x0026
R
DBGTBL
W
Bit 7
R ¹ TBF
DBGCNT
W
R
0
0x0027 DBGSCRX
W
R
0
0x0027 DBGMFR
W
2 _0x0028
3 _0x0028
4 _0x0028
R
DBGACTL
W
R
DBGBCTL
W
R
DBGCCTL
W
SZE
SZE
0
R
0
0x0029 DBGXAH
W
R
0x002A DBGXAM
Bit 15
W
0x002B
R
DBGXAL
W
Bit 7
6
0
TRIG
0
TSOURCE
0
Bit 14
Bit 6
0
0
0
SZ
SZ
0
0
14
6
5
0
0
0
0
Bit 13
Bit 5
0
0
TAG
TAG
TAG
0
13
5
4
BDM
0
3
DBGBRK
0
2
0
SSF2
0
TRCMOD
0
0
0
Bit 12
Bit 11
Bit 10
Bit 4
Bit 3
Bit 2
CNT
0
SC3
SC2
0
0
MC2
BRK
RW
RWE
BRK
RW
RWE
BRK
RW
RWE
0
0
0
12
11
10
4
3
2
1
Bit 0
COMRV
SSF1
SSF0
0
TALIGN
ABCM
Bit 9
Bit 8
Bit 1
Bit 0
SC1
MC1
SC0
MC0
NDB
0
0
COMPE
COMPE
COMPE
Bit 17
Bit 16
9
Bit 8
1
Bit 0
Figure 8-2. Quick Reference to DBG Registers
MC9S12G Family Reference Manual, Rev.1.23
316
Freescale Semiconductor