S9S12G128F0MLL Datasheet, PDF (244/1292 Pages) Freescale Semiconductor, Inc – Reference Manual and Date Sheet

Port Integration Module (S12GPIMV1)
2.4.3.61 Port AD Interrupt Enable Register (PIE0AD)
Read: Anytime
Address 0x027C (G1, G2)
7
R
PIE0AD7
W
Reset
0
Address 0x027C (G3)
6
PIE0AD6
0
5
PIE0AD5
0
4
PIE0AD4
0
3
PIE0AD3
0
2
PIE0AD2
0
7
R
0
W
Reset
0
1 _{Read: Anytime}
Write: Anytime
6
5
4
3
2
0
0
0
PIE0AD3 PIE0AD2
0
0
0
0
0
Figure 2-60. Port AD Interrupt Enable Register (PIE0AD)
Access: User read/write¹
1
0
PIE0AD1 PIE0AD0
0
0
Access: User read/write¹
1
0
PIE0AD1 PIE0AD0
0
0
Table 2-87. PIE0AD Register Field Descriptions
Field
Description
7-0 Port AD interrupt enable—
PIE0AD This bit enables or disables the edge sensitive pin interrupt on the associated pin. An interrupt can be generated if
the pin is operating in input or output mode when in use with the general-purpose or related peripheral function.
1 Interrupt is enabled
0 Interrupt is disabled (interrupt flag masked)
2.4.3.62 Port AD Interrupt Enable Register (PIE1AD)
Read: Anytime
Address 0x027D
7
R
PIE1AD7
W
Reset
0
1 _{Read: Anytime}
Write: Anytime
6
PIE1AD6
5
PIE1AD5
4
PIE1AD4
3
PIE1AD3
2
PIE1AD2
0
0
0
0
0
Figure 2-61. Port AD Interrupt Enable Register (PIE1AD)
Access: User read/write¹
1
0
PIE1AD1 PIE1AD0
0
0
MC9S12G Family Reference Manual, Rev.1.23
246
Freescale Semiconductor