S9S12G128F0MLL Datasheet, PDF (324/1292 Pages) Freescale Semiconductor, Inc – Reference Manual and Date Sheet

S12S Debug Module (S12SDBGV2)
SC[3:0]
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Table 8-20. State3 — Sequencer Next State Selection
Description (Unspecified matches have no effect)
Match2 to State2........ Match1 to Final State
Match0 to Final State....... Match1 to State1
Match1 to Final State....... Match2 to State1
Match1 to State2
Match1 to Final State
Match2 to State2........ Match0 to Final State
Match0 to Final State
Reserved
Reserved
Either Match1 or Match2 to State1....... Match0 to Final State
Reserved
Reserved
Either Match1 or Match2 to Final State....... Match0 to State1
Match0 to State2....... Match2 to Final State
Reserved
The priorities described in Table 8-36 dictate that in the case of simultaneous matches, a match leading to
final state has priority followed by the match on the lower channel number (0,1,2).
8.3.2.7.4 Debug Match Flag Register (DBGMFR)
Address: 0x0027
7
R
0
W
Reset
0
6
5
4
3
2
0
0
0
0
MC2
0
0
0
0
0
= Unimplemented or Reserved
Figure 8-12. Debug Match Flag Register (DBGMFR)
1
MC1
0
0
MC0
0
Read: If COMRV[1:0] = 11
Write: Never
DBGMFR is visible at 0x0027 only with COMRV[1:0] = 11. It features 3 flag bits each mapped directly
to a channel. Should a match occur on the channel during the debug session, then the corresponding flag
is set and remains set until the next time the module is armed by writing to the ARM bit. Thus the contents
are retained after a debug session for evaluation purposes. These flags cannot be cleared by software, they
are cleared only when arming the module. A set flag does not inhibit the setting of other flags. Once a flag
is set, further comparator matches on the same channel in the same session have no affect on that flag.
8.3.2.8 Comparator Register Descriptions
Each comparator has a bank of registers that are visible through an 8-byte window in the DBG module
register address map. Comparator A consists of 8 register bytes (3 address bus compare registers, two data
bus compare registers, two data bus mask registers and a control register). Comparator B consists of four
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