S9S12G128F0MLL Datasheet, PDF (235/1292 Pages) Freescale Semiconductor, Inc – Reference Manual and Date Sheet

Port Integration Module (S12GPIMV1)
2.4.3.46 Port J Polarity Select Register (PPSJ)
Address 0x026D (G1, G2)
7
R
PPSJ7
W
Reset
0
Address 0x026D (G3)
6
PPSJ6
0
5
PPSJ5
0
4
PPSJ4
0
3
PPSJ3
0
2
PPSJ2
0
7
R
0
W
Reset
0
1 _{Read: Anytime}
Write: Anytime
6
5
4
3
2
0
0
0
PPSJ3
PPSJ2
0
0
0
0
0
Figure 2-46. Port J Polarity Select Register (PPSJ)
Access: User read/write¹
1
0
PPSJ1
PPSJ0
0
0
Access: User read/write¹
1
0
PPSJ1
PPSJ0
0
0
Table 2-72. PPSJ Register Field Descriptions
Field
7-0
PPSJ
Description
Port J pull device select—Configure pull device and pin interrupt edge polarity on input pin
This bit selects a pullup or a pulldown device if enabled on the associated port input pin.
This bit also selects the polarity of the active pin interrupt edge.
1 Pulldown device selected; rising edge selected
0 Pullup device selected; falling edge selected
2.4.3.47 Port J Interrupt Enable Register (PIEJ)
Read: Anytime
Address 0x026E (G1, G2)
7
R
PIEJ7
W
Reset
0
Address 0x026E (G3)
6
PIEJ6
0
5
PIEJ5
0
4
PIEJ4
0
3
PIEJ3
0
2
PIEJ2
0
7
R
0
W
Reset
0
6
5
4
3
2
0
0
0
PIEJ3
PIEJ2
0
0
0
0
0
Figure 2-47. Port J Interrupt Enable Register (PIEJ)
Access: User read/write¹
1
0
PIEJ1
PIEJ0
0
0
Access: User read/write¹
1
0
PIEJ1
PIEJ0
0
0
MC9S12G Family Reference Manual, Rev.1.23
Freescale Semiconductor
237