S9S12G128F0MLL Datasheet, PDF (648/1292 Pages) Freescale Semiconductor, Inc – Reference Manual and Date Sheet

Pulse-Width Modulator (S12PWM8B8CV2)
The clock source of each PWM channel is determined by PCLKx bits in PWMCLK (see Section 19.3.2.3,
“PWM Clock Select Register (PWMCLK)) and PCLKABx bits in PWMCLKAB as shown in Table 19-5
and Table 19-6.
19.3.2.8 PWM Scale A Register (PWMSCLA)
PWMSCLA is the programmable scale value used in scaling clock A to generate clock SA. Clock SA is
generated by taking clock A, dividing it by the value in the PWMSCLA register and dividing that by two.
Clock SA = Clock A / (2 * PWMSCLA)
NOTE
When PWMSCLA = $00, PWMSCLA value is considered a full scale value
of 256. Clock A is thus divided by 512.
Any value written to this register will cause the scale counter to load the new scale value (PWMSCLA).
Module Base + 0x0008
7
6
5
4
3
2
1
0
R
Bit 7
6
5
4
3
2
1
Bit 0
W
Reset
0
0
0
0
0
0
0
0
Figure 19-10. PWM Scale A Register (PWMSCLA)
Read: Anytime
Write: Anytime (causes the scale counter to load the PWMSCLA value)
19.3.2.9 PWM Scale B Register (PWMSCLB)
PWMSCLB is the programmable scale value used in scaling clock B to generate clock SB. Clock SB is
generated by taking clock B, dividing it by the value in the PWMSCLB register and dividing that by two.
Clock SB = Clock B / (2 * PWMSCLB)
NOTE
When PWMSCLB = $00, PWMSCLB value is considered a full scale value
of 256. Clock B is thus divided by 512.
Any value written to this register will cause the scale counter to load the new scale value (PWMSCLB).
Module Base + 0x0009
7
6
5
4
3
2
1
0
R
Bit 7
6
5
4
3
2
1
Bit 0
W
Reset
0
0
0
0
0
0
0
0
Figure 19-11. PWM Scale B Register (PWMSCLB)
Read: Anytime
Write: Anytime (causes the scale counter to load the PWMSCLB value).
MC9S12G Family Reference Manual, Rev.1.23
650
Freescale Semiconductor