MC9RS08KA2 Datasheet, PDF (78/132 Pages) Freescale Semiconductor, Inc – Microcontrollers

Internal Clock Source (RS08ICSV1)
9.4.4 ICS Status and Control (ICSSC)
7
R
0
W
6
5
4
0
0
0
3
2
1
0
0
CLKST
0
FTRIM
POR:
0
0
0
0
0
0
0
0
Reset:
0
0
0
0
0
0
0
U
= Unimplemented
Figure 9-6. ICS Status and Control Register (ICSSC)
Table 9-5. ICSSC Field Descriptions
Field
2
CLKST
0
FTRIM
Description
Clock Mode Status — The CLKST read-only bit indicate the current clock mode. The CLKST bit does not update
immediately after a write to the CLKS bit due to internal synchronization between clock domains.
0 Output of FLL is selected
1 Internal reference clock is selected
ICS Fine Trim — The FTRIM bit controls the smallest adjustment of the internal reference clock frequency.
Setting FTRIM will increase the period and clearing FTRIM will decrease the period by the smallest amount
possible.
9.5 Functional Description
9.5.1 Operational Modes
The states of the ICS are shown as a state diagram and are described in this section. The arrows indicate
the allowed movements between the states.
CLKS=0
FLL Engaged
Internal (FEI)
CLKS=1
LP=0
FLL Bypassed
Internal (FBI)
CLKS=1
LP=1
FLL Bypassed
Internal Low
Power(FBILP)
Stop^{1, 2}
1 _{ICS enters its Stop state when MCU enters stop, FLL is always disabled. ICS returns to the state that}
was active before MCU entered stop, unless a reset occurs while in stop.
2 _{If IREFSTEN is set when MCU enters stop, the ICSIRCLK remains running.}
Figure 9-7. Clock Switching Modes
MC9RS08KA2 Series Data Sheet, Rev. 2
78
Freescale Semiconductor