MC9RS08KA2 Datasheet, PDF (69/132 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 8 Central Processor Unit (RS08CPUV1)
Table 8-1. Instruction Set Summary (Sheet 3 of 5)
Source
Form
BSET n,opr8a
BSET n,D[X]
BSET n,X
BSR rel
CBEQA #opr8i,rel
CBEQ opr8a,rel
CBEQ ,X,rel ^(1),(2)
CBEQ X,rel ⁽¹⁾
CLC
CLR opr8a
CLR opr5a
CLR ,X ⁽¹⁾
CLRA
CLRX ⁽¹⁾
CMP #opr8i
CMP opr8a
CMP ,X ⁽¹⁾
CMP X ⁽¹⁾
COMA
DBNZ opr8a,rel
DBNZ ,X,rel ⁽¹⁾
DBNZA rel
DBNZX rel ⁽¹⁾
DEC opr8a
DEC opr4a
DEC ,X ⁽¹⁾
DECA
DEC X
EOR #opr8i
EOR opr8a
EOR ,X ⁽¹⁾
EOR X
Description
Set Bit n in Memory
Branch Subroutine
Compare and Branch if
Equal
Clear Carry Bit
Clear
Compare Accumulator
with Memory
Complement
(One’s Complement)
Decrement and Branch if
Not Zero
Decrement
Exclusive OR
Memory with
Accumulator
Operation
Mn ← 1
PC ← (PC) + 2
Push PC to shadow PC
PC ← (PC) + rel
PC ← (PC) + $0003 + rel, if (A) – (M) = $00
PC ← (PC) + $0003 + rel, if (A) – (M) = $00
PC ← (PC) + $0003 + rel, if (A) – (X) = $00
C←0
M ← $00
A ← $00
X ← $00
(A) – (M)
(A) – (X)
A ← (A)
A ←(A) – $01 or M ←(M) - $01
PC ← (PC) + $0003 + rel if (result) ≠ 0 for DBNZ
direct
PC ← (PC) + $0002 + rel if (result) ≠ 0 for
DBNZA
X ←(X) – $01
PC ← (PC) + $0003 + rel if (result) ≠ 0
M ← (M) – $01
A ← (A) – $01
X ← (X) – $01
A ← (A ⊕ M)
A ← (A ⊕ X)
Effect
on
CCR
ZC
––
––
––
–0
1–
↕↕
↕1
––
↕–
↕–
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
IX (b0)
IX (b1)
IX (b2)
IX (b3)
IX (b4)
IX (b5)
IX (b6)
IX (b7)
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
REL
IMM
DIR
IX
DIR
INH
DIR
SRT
IX
INH
INH
IMM
DIR
IX
INH
INH
DIR
IX
INH
INH
DIR
TNY
IX
INH
DIR
IMM
DIR
IX
DIR
10 dd
5
12 dd
5
14 dd
5
16 dd
5
18 dd
5
1A dd
5
1C dd
5
1E dd
5
10 0E
5
12 0E
5
14 0E
5
16 0E
5
18 0E
5
1A 0E
5
1C 0E
5
1E 0E
5
10 0F
5
12 0F
5
14 0F
5
16 0F
5
18 0F
5
1A 0F
5
1C 0F
5
1E 0F
5
AD rr
3
41 ii rr 4
31 dd rr 5
31 0E rr 5
31 0F rr
5
38
1
3F dd
3
8x / 9x
2
8E
2
4F
1
8F
2
A1 ii
2
B1 dd
3
B1 0E
3
B1 0F
3
43
1
3B dd rr 7
3B 0E rr
7
4B rr
4
3B 0F rr
7
3A dd
5
5x
4
5E
4
4A
1
5F
4
A8 ii
2
B8 dd
3
B8 0E
3
B8 0F
3
1. This is a pseudo instruction supported by the normal RS08 instruction set.
2. This instruction is different from that of the HC08 and HCS08 in that the RS08 does not auto-increment the index register.
MC9RS08KA2 Series Data Sheet, Rev. 2
Freescale Semiconductor
69