MC9RS08KA2 Datasheet, PDF (77/132 Pages) Freescale Semiconductor, Inc – Microcontrollers

9.4.2 ICS Control Register 2 (ICSC2)
Internal Clock Source (RS08ICSV1)
7
6
5
4
3
2
1
0
R
BDIV
W
0
0
0
0
0
LP
Reset:
0
1
0
0
0
0
0
0
= Unimplemented
Figure 9-4. ICS Control Register 2 (ICSC2)
Table 9-3. ICSC2 Field Descriptions
Field
7:6
BDIV
3
LP
Description
Bus Frequency Divider — Selects the amount to divide down the clock source selected by the CLKS bit. This
controls the bus frequency.
00 Encoding 0 — Divides selected clock by 1
01 Encoding 1 — Divides selected clock by 2 (reset default)
10 Encoding 2 — Divides selected clock by 4
11 Encoding 3 — Divides selected clock by 8
Low Power Select — Controls whether the FLL is disabled in FLL bypassed modes.
1 FLL is disabled in bypass modes
0 FLL is not disabled in bypass mode
9.4.3 ICS Trim Register (ICSTRM)
7
R
W
POR:
1
Reset:
U
6
5
4
3
TRIM
2
1
0
0
0
0
0
0
0
0
U
U
U
U
U
U
U
Figure 9-5. ICS Trim Register (ICSTRM)
Table 9-4. ICSTRM Field Descriptions
Field
7:0
TRIM
Description
ICS Trim Setting — The TRIM bits control the internal reference clock frequency by controlling the internal
reference clock period. The bits’ effect are binary weighted (i.e., bit 1 will adjust twice as much as bit 0).
Increasing the binary value in TRIM will increase the period, and decreasing the value will decrease the period.
An additional fine trim bit is available in ICSSC as the FTRIM bit.
MC9RS08KA2 Series Data Sheet, Rev. 2
Freescale Semiconductor
77