MC9RS08KA2 Datasheet, PDF (40/132 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 5 Resets, Interrupts, and General System Control
Table 5-3. SOPT Register Field Descriptions
Field
Description
7
COPE
COP Watchdog Enable — This write-once bit selects whether the COP watchdog is enabled.
0 COP watchdog timer disabled.
1 COP watchdog timer enabled (force reset on timeout).
6
COPT
COP Watchdog Timeout — This write-once bit selects the timeout period of the COP.
0 Short timeout period selected.
1 Long timeout period selected.
5
STOPE
Stop Mode Enable — This write-once bit is used to enable stop mode. If stop mode is disabled and a user
program attempts to execute a STOP instruction, an illegal opcode reset is forced.
0 Stop mode disabled.
1 Stop mode enabled.
1
BKGDPE^1,2
Background Debug Mode Pin Enable — This write-once bit when set enables the PTA3/ACMPO/BKGD/MS
pin to function as BKGD/MS. When clear, the pin functions as one of its output only alternative functions. This
pin defaults to the BKGD/MS function following any MCU reset.
0 PTA3/ACMPO/BKGD/MS pin functions as PTA3 or ACMPO.
1 PTA3/ACMPO/BKGD/MS pin functions as BKGD/MS.
0
RSTPE
RESET Pin Enable — When set, this write-once bit enables the PTA2/KBIP2/TCLK/RESET/V_PP pin to function
as RESET. When clear, the pin functions as one of its input-only alternative functions. This pin is input-only port
function following an MCU POR. When RSTPE is set, an internal pullup device is enabled on RESET.
0 PTA2/KBIP2/TCLK/RESET/V_PP pin functions as PTA2/KBIP2/TCLK/V_PP.
1 PTA2/KBIP2/TCLK/RESET/V_PP pin functions as RESET/V_PP.
1 _{When the device is reset into normal operating mode (MS is high during reset), BKGDPE is reset to 1 if Flash security is}
disengaged (SECD = 1); BKGDPE is reset to 0 if Flash security is engaged (SECD = 0). When the device is reset into active
BDM mode (MS is low during reset), BKGDPE is always reset to 1 such that BDM communication is allowed.
2 _{BKGDPE can only write once from value 1 to 0. Writing from value 0 to 1 by user software is not allowed. BKGDPE can be}
changed back to 1 only by a POR or reset with proper condition as stated in Note 1.
5.8.3 System Device Identification Register (SDIDH, SDIDL)
These high page read-only registers are included so host development systems can identify the RS08
derivative and revision number. This allows the development software to recognize where specific memory
blocks, registers, and control bits are located in a target MCU.
7
6
5
4
3
2
1
0
R REV3
REV2
REV1
REV0
ID11
ID10
ID9
ID8
W
Reset: 0 (Note 1) 0 (Note 1) 0 (Note 1) 0 (Note 1)
1
0
0
0
= Unimplemented or Reserved
1. The revision number that is hard coded into these bits reflects the current silicon revision level.
Figure 5-3. System Device Identification Register — High (SDIDH)
MC9RS08KA2 Series Data Sheet, Rev. 2
40
Freescale Semiconductor