MC9RS08KA2 Datasheet, PDF (38/132 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 5 Resets, Interrupts, and General System Control
for applications requiring more accurate real-time interrupts. The RTICLKS bit in SRTISC is used to select
the RTI clock source. Both the1-kHz and 32-kHz clock sources for the RTI can be used when the MCU is
in run, wait or stop mode. For the 32-kHz clock source to run in stop, the LVDE and LVDSE bits in the
SPMSC1 must both be set before entering stop.
The SRTISC register includes a read-only status flag, a write-only acknowledge bit, and a 3-bit control
value (RTIS) used to select one of seven wakeup periods or disable RTI. The RTI has a local interrupt
enable, RTIE, to allow masking of the real-time interrupt. The RTI can be disabled by writing each bit of
RTIS to 0s, and no interrupts will be generated. See Section 5.8.4, “System Real-Time Interrupt Status and
Control Register (SRTISC),” for detailed information about this register.
5.8 Reset, Interrupt, and System Control Registers and Control Bits
Refer to the direct-page register summary in Chapter 4, “Memory,” for the absolute address assignments
for all registers. This section refers to registers and control bits only by their names. A Freescale-provided
equate or header file is used to translate these names into the appropriate absolute addresses.
Some control bits in the SOPT register are related to modes of operation. Although brief descriptions of
these bits are provided here, the related functions are discussed in greater detail in Chapter 3, “Modes of
Operation”.
5.8.1 System Reset Status Register (SRS)
This high page register includes read-only status flags to indicate the source of the most recent reset. When
a debug host forces reset by the BDC_RESET command, all of the status bits in SRS will be cleared.
Writing any value to this register address clears the COP watchdog timer without affecting the contents of
this register. The reset state of these bits depends on what caused the MCU to reset.
7
6
5
4
3
2
1
0
R POR
PIN
COP
ILOP
ILAD
0
LVD
0
W
Writing any value to SRS address clears COP watchdog timer.
POR:
1
0
0
0
0
0
1
0
LVR:
0
0
0
0
0
0
1
0
Any other
0
Note 1
Note 1
Note 1
Note 1
0
0
0
reset:
1. Any of these reset sources that are active at the time of reset entry will cause the corresponding bit(s) to be set; bits
corresponding to sources that are not active at the time of reset entry will be cleared.
Figure 5-1. System Reset Status (SRS)
MC9RS08KA2 Series Data Sheet, Rev. 2
38
Freescale Semiconductor