MC9RS08KA2 Datasheet, PDF (72/132 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 8 Central Processor Unit (RS08CPUV1)
Table 8-2. Opcode Map
DIR
DIR
TNY DIR/REL INH
TNY
TNY
TNY
SRT
SRT IMM/INH DIR/EXT SRT
SRT
SRT
SRT
HIGH
0
1
2
3
LOW
5
5
4
3
0 BRSET0 BSET0 INC
BRA
3 DIR 2 DIR 1 TNY 2 REL
4
5
6
7
8
9
A
B
C
D
E
F
4
3
3
2
2
2
3
3
3
2
2
DEC ADD SUB CLR CLR SUB SUB LDA
LDA
STA
STA
1 TNY 1 TNY 1 TNY 1 SRT 1 SRT 2 IMM 2 DIR 1 SRT 1 SRT 1 SRT 1 SRT
5
5
4
5
4
4
3
3
2
2
2
3
3
3
2
2
1 BRCLR0 BCLR0 INC CBEQ CBEQA DEC ADD SUB CLR CLR CMP CMP LDA
LDA
STA
STA
3 DIR 2 DIR 1 TNY 3 DIR 3 IMM 1 TNY 1 TNY 1 TNY 1 SRT 1 SRT 2 IMM 2 DIR 1 SRT 1 SRT 1 SRT 1 SRT
5
5
4
2 BRSET1 BSET1 INC
3 DIR 2 DIR 1 TNY
1
4
3
3
2
2
2
3
3
3
2
2
SLA DEC ADD SUB CLR CLR SBC SBC LDA
LDA
STA
STA
1 INH 1 TNY 1 TNY 1 TNY 1 SRT 1 SRT 2 IMM 2 DIR 1 SRT 1 SRT 1 SRT 1 SRT
5
5
4
3 BRCLR1 BCLR1 INC
3 DIR 2 DIR 1 TNY
1
4
3
3
2
2
COMA DEC ADD SUB CLR CLR
1 INH 1 TNY 1 TNY 1 TNY 1 SRT 1 SRT
3
3
2
2
LDA
LDA
STA
STA
1 SRT 1 SRT 1 SRT 1 SRT
5
5
4
3
1
4
3
3
2
2
2
3
3
3
2
2
4 BRSET2 BSET2 INC BCC LSRA DEC ADD SUB CLR CLR AND AND LDA
LDA
STA
STA
3 DIR 2 DIR 1 TNY 2 REL 1 INH 1 TNY 1 TNY 1 TNY 1 SRT 1 SRT 2 IMM 2 DIR 1 SRT 1 SRT 1 SRT 1 SRT
5
5
4
3
1
4
3
3
2
2
5 BRCLR2 BCLR2 INC
BCS
SHA
DEC ADD SUB
CLR
CLR
3 DIR 2 DIR 1 TNY 2 REL 1 INH 1 TNY 1 TNY 1 TNY 1 SRT 1 SRT
3
3
2
2
LDA
LDA
STA
STA
1 SRT 1 SRT 1 SRT 1 SRT
5
5
4
3
1
4
3
3
2
2
2
3
3
3
2
2
6 BRSET3 BSET3 INC
BNE RORA DEC ADD SUB CLR CLR LDA
LDA
LDA
LDA
STA
STA
3 DIR 2 DIR 1 TNY 2 REL 1 INH 1 TNY 1 TNY 1 TNY 1 SRT 1 SRT 2 IMM 2 DIR 1 SRT 1 SRT 1 SRT 1 SRT
5
5
4
3
7 BRCLR3 BCLR3 INC BEQ
3 DIR 2 DIR 1 TNY 2 REL
4
3
3
2
2
DEC ADD SUB CLR CLR
1 TNY 1 TNY 1 TNY 1 SRT 1 SRT
3
3
3
2
2
STA
LDA
LDA
STA
STA
2 DIR 1 SRT 1 SRT 1 SRT 1 SRT
5
5
4
1
1
4
3
3
2
2
2
3
3
3
2
2
8 BRSET4 BSET4 INC
CLC LSLA DEC ADD SUB CLR CLR EOR EOR LDA
LDA
STA
STA
3 DIR 2 DIR 1 TNY 1 INH 1 INH 1 TNY 1 TNY 1 TNY 1 SRT 1 SRT 2 IMM 2 DIR 1 SRT 1 SRT 1 SRT 1 SRT
5
5
4
1
1
4
3
3
2
2
2
3
3
3
2
2
9 BRCLR4 BCLR4 INC
SEC ROLA DEC ADD SUB CLR CLR ADC ADC LDA
LDA
STA
STA
3 DIR 2 DIR 1 TNY 1 INH 1 INH 1 TNY 1 TNY 1 TNY 1 SRT 1 SRT 2 IMM 2 DIR 1 SRT 1 SRT 1 SRT 1 SRT
5
5
4
5
1
4
3
3
2
2
2
3
3
3
2
2
A BRSET5 BSET5 INC DEC DECA DEC ADD SUB CLR CLR ORA ORA LDA
LDA
STA
STA
3 DIR 2 DIR 1 TNY 2 DIR 1 INH 1 TNY 1 TNY 1 TNY 1 SRT 1 SRT 2 IMM 2 DIR 1 SRT 1 SRT 1 SRT 1 SRT
5
5
4
6
4
4
3
3
2
2
2
3
3
3
2
2
B BRCLR5 BCLR5 INC DBNZ DBNZA DEC ADD SUB CLR CLR ADD ADD LDA
LDA
STA
STA
3 DIR 2 DIR 1 TNY 3 DIR 2 INH 1 TNY 1 TNY 1 TNY 1 SRT 1 SRT 2 IMM 2 DIR 1 SRT 1 SRT 1 SRT 1 SRT
5
5
4
5
1
4
3
3
2
2
1
4
3
3
2
2
C BRSET6 BSET6 INC
INC INCA DEC ADD SUB CLR CLR NOP JMP LDA
LDA
STA
STA
3 DIR 2 DIR 1 TNY 2 DIR 1 INH 1 TNY 1 TNY 1 TNY 1 SRT 1 SRT 1 INH 3 EXT 1 SRT 1 SRT 1 SRT 1 SRT
5
5
4
D BRCLR6 BCLR6 INC
3 DIR 2 DIR 1 TNY
4
3
3
2
2
3
4
3
3
2
2
DEC ADD SUB CLR CLR BSR JSR
LDA
LDA
STA
STA
1 TNY 1 TNY 1 TNY 1 SRT 1 SRT 2 REL 3 EXT 1 SRT 1 SRT 1 SRT 1 SRT
5
5
4
4
5
4
3
3
2
2
2+
3
3
3
2
2
E BRSET7 BSET7 INC MOV MOV DEC ADD SUB CLR CLR STOP RTS LDA
LDA
STA
STA
3 DIR 2 DIR 1 TNY 3 IMD 3 DD 1 TNY 1 TNY 1 TNY 1 SRT 1 SRT 1 INH 1 INH 1 SRT 1 SRT 1 SRT 1 SRT
5
5
4
3
1
4
3
3
2
2
2+
5+
3
3
2
2
F BRCLR7 BCLR7 INC
CLR CLRA DEC ADD SUB CLR CLR WAIT BGND LDA
LDA
STA
STA
3 DIR 2 DIR 1 TNY 2 DIR 1 INH 1 TNY 1 TNY 1 TNY 1 SRT 1 SRT 1 INH 1 INH 1 SRT 1 SRT 1 SRT 1 SRT
INH Inherent
IMM Immediate
DIR Direct
EXT Extended
DD Direct-Direct
REL
SRT
TNY
IMD
Relative
Short
Tiny
Immediate-Direct
High Byte of Opcode in Hexadecimal
B
Gray box is decoded as illegal instruction
3 RS08 Cycles
Low Byte of Opcode in Hexadecimal
0
SUB Opcode Mnemonic
2 DIR ^{Number of Bytes /}
Addressing Mode
MC9RS08KA2 Series Data Sheet, Rev. 2
72
Freescale Semiconductor