MC9RS08KA2 Datasheet, PDF (76/132 Pages) Freescale Semiconductor, Inc – Microcontrollers

Internal Clock Source (RS08ICSV1)
9.4 Register Definition
Table 9-1 is a summary of ICS registers.
Table 9-1. ICS Register Summary
Name
7
6
5
R
0
0
ICSC1
CLKS
W
R
0
ICSC2
BDIV
W
R
ICSTRM
W
R
0
0
0
ICSSC
W
4
3
0
0
0
LP
TRIM
0
0
2
0
0
CLKST
9.4.1 ICS Control Register 1 (ICSC1)
1
0
0
IREFSTEN
0
0
0
FTRIM
7
6
5
4
3
2
R
0
0
0
0
0
CLKS
W
Reset:
0
0
0
0
0
0
= Unimplemented
Figure 9-3. ICS Control Register 1 (ICSC1)
1
0
0
IREFSTEN
0
0
Table 9-2. ICSC1 Field Descriptions
Field
Description
6
CLKS
Clock Source Select — Selects the clock source that controls the bus frequency. The actual bus frequency
depends on the value of the BDIV bits.
0 Output of FLL is selected
1 Internal reference clock is selected
0
IREFSTEN
Internal Reference Stop Enable — Controls whether the internal reference clock remains enabled when the
ICS enters stop mode.
1 Internal reference clock remains enabled in stop
0 Internal reference clock is disabled in stop
MC9RS08KA2 Series Data Sheet, Rev. 2
76
Freescale Semiconductor