MC9RS08KA2 Datasheet, PDF (64/132 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 8 Central Processor Unit (RS08CPUV1)
• Reset events force the CPU to start over at the beginning of the application program, which forces
execution to start at $3FFD.
• A host development system can cause the CPU to go to active background mode rather than
continuing to the next instruction in the application program.
8.4.1 Reset Sequence
Processing begins at the trailing edge of a reset event. The number of things that can cause reset events can
vary slightly from one RS08 derivative to another; however, the most common sources are: power-on reset,
the external RESET pin, low-voltage reset, COP watchdog timeout, illegal opcode detect, and illegal
address access. For more information about how the MCU recognizes reset events and determines the
difference between internal and external causes, refer to the Resets and Interrupts chapter.
Reset events force the MCU to immediately stop what it is doing and begin responding to reset. Any
instruction that was in process will be aborted immediately without completing any remaining clock
cycles. A short sequence of activities is completed to decide whether the source of reset was internal or
external and to record the cause of reset. For the remainder of the time, the reset source remains active and
the internal clocks are stopped to save power. At the trailing edge of the reset event, the clocks resume and
the CPU exits from the reset condition. The program counter is reset to $3FFD and an instruction fetch
will be started after the release of reset.
For the device to execute code from the on-chip memory starting from $3FFD after reset, care should be
taken to not force the BKDG pin low on the end of reset because this will force the device into active
background mode where the CPU will wait for a command from the background communication interface.
8.4.2 Interrupts
The interrupt mechanism in RS08 is not used to interrupt the normal flow of instructions; it is used to wake
up the RS08 from wait and stop modes. In run mode, interrupt events must be polled by the CPU. The
interrupt feature is not compatible with Freescale’s HC05, HC08, or HCS08 Families.
8.4.3 Wait and Stop Mode
Wait and stop modes are entered by executing a WAIT or STOP instruction, respectively. In these modes,
the clocks to the CPU are shut down to save power and CPU activity is suspended. The CPU remains in
this low-power state until an interrupt or reset event wakes it up. Please refer to the Resets and Interrupts
chapter for the effects of wait and stop on other device peripherals.
8.4.4 Active Background Mode
Active background mode refers to the condition in which the CPU has stopped executing user program
instructions and is waiting for serial commands from the background debug system. Refer to the
Development Support chapter for detailed information on active background mode.
The arithmetic left shift pseudo instruction is also available because its operation is identical to logical shift
left.
MC9RS08KA2 Series Data Sheet, Rev. 2
64
Freescale Semiconductor