MC9RS08KA2 Datasheet, PDF (68/132 Pages) Freescale Semiconductor, Inc – Microcontrollers

Chapter 8 Central Processor Unit (RS08CPUV1)
Table 8-1. Instruction Set Summary (Sheet 2 of 5)
Source
Form
Description
BRCLR n,opr8a,rel
BRCLR n,D[X],rel
Branch if Bit n in Memory
Clear
BRCLR n,X,rel
BRSET n,opr8a,rel
BRSET n,D[X],rel
Branch if Bit n in Memory
Set
BRSET n,X,rel
Operation
PC ← (PC) + $0003 + rel, if (Mn) = 0
PC ← (PC) + $0003 + rel, if (Mn) = 1
Effect
on
CCR
ZC
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
IX (b0)
IX (b1)
IX (b2)
–
↕
IX (b3)
IX (b4)
IX (b5)
IX (b6)
IX (b7)
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
IX (b0)
IX (b1)
IX (b2)
–
↕
IX (b3)
IX (b4)
IX (b5)
IX (b6)
IX (b7)
DIR (b0)
DIR (b1)
DIR (b2)
DIR (b3)
DIR (b4)
DIR (b5)
DIR (b6)
DIR (b7)
01 dd rr 5
03 dd rr 5
05 dd rr 5
07 dd rr 5
09 dd rr 5
0B dd rr 5
0D dd rr 5
0F dd rr 5
01 0E rr 5
03 0E rr 5
05 0E rr 5
07 0E rr 5
09 0E rr 5
0B 0E rr 5
0D 0E rr 5
0F 0E rr 5
01 0F rr
5
03 0F rr
5
05 0F rr
5
07 0F rr
5
09 0F rr
5
0B 0F rr
5
0D 0F rr
5
0F 0F rr
5
00 dd rr 5
02 dd rr 5
04 dd rr 5
06 dd rr 5
08 dd rr 5
0A dd rr 5
0C dd rr 5
0E dd rr 5
00 0E rr 5
02 0E rr 5
04 0E rr 5
06 0E rr 5
08 0E rr 5
0A 0E rr 5
0C 0E rr 5
0E 0E rr 5
00 0F rr
5
02 0F rr
5
04 0F rr
5
06 0F rr
5
08 0F rr
5
0A 0F rr
5
0C 0F rr
5
0E 0F rr
5
1. This is a pseudo instruction supported by the normal RS08 instruction set.
2. This instruction is different from that of the HC08 and HCS08 in that the RS08 does not auto-increment the index register.
MC9RS08KA2 Series Data Sheet, Rev. 2
68
Freescale Semiconductor