K61P256M120SF3 Datasheet, PDF (77/90 Pages) Freescale Semiconductor, Inc – K61 Sub-Family Data Sheet

Pinout
7.1 Obtaining package dimensions
Package dimensions are provided in package drawings.
To find a package drawing, go to http://www.freescale.com and perform a keyword
search for the drawing’s document number:
If you want the drawing for this package
256-pin MAPBGA
Then use this document number
98ASA00346D
8 Pinout
8.1 K61 Signal Multiplexing and Pin Assignments
The following table shows the signals available on each pin and the locations of these
pins on the devices supported by this document. The Port Control Module is responsible
for selecting which ALT functionality is available on each pin.
256 Pin Name Default
ALT0
ALT1
ALT2
ALT3
ALT4
ALT5
ALT6
ALT7
EzPort
MAP
BGA
E2 PTE0
ADC1_SE4a ADC1_SE4a PTE0
SPI1_PCS1 UART1_TX SDHC0_D1
I2C1_SDA RTC_CLKO
UT
F2 PTE1/
ADC1_SE5a ADC1_SE5a PTE1/
SPI1_SOUT UART1_RX SDHC0_D0
LLWU_P0
LLWU_P0
I2C1_SCL SPI1_SIN
F3 PTE2/
ADC1_SE6a ADC1_SE6a PTE2/
SPI1_SCK UART1_CTS SDHC0_DCL
LLWU_P1
LLWU_P1
_b
K
G2 PTE3
ADC1_SE7a ADC1_SE7a PTE3
SPI1_SIN UART1_RTS SDHC0_CM
_b
D
SPI1_SOUT
G7 VDD
VDD
VDD
H7 VDDINT VDDINT VDDINT
H8 VSS
VSS
VSS
F1 PTF17
DISABLED
PTF17
SPI2_SCK FTM0_CH4 UART0_RX
G1 PTF18
DISABLED
PTF18
SPI2_SOUT FTM1_CH0 UART0_TX
G3 PTE4/
DISABLED
LLWU_P2
PTE4/
SPI1_PCS0 UART3_TX SDHC0_D3
LLWU_P2
G4 PTE5
DISABLED
PTE5
SPI1_PCS2 UART3_RX SDHC0_D2
FTM3_CH0
H2 PTE6
DISABLED
PTE6
SPI1_PCS3 UART3_CTS I2S0_MCLK
_b
FTM3_CH1 USB_SOF_
OUT
H1 PTF19
DISABLED
PTF19
SPI2_SIN FTM1_CH1 UART5_RX
H5 PTF20
DISABLED
PTF20
SPI2_PCS1 FTM2_CH0 UART5_TX
K61 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
Freescale Semiconductor, Inc.
Preliminary
77