K61P256M120SF3 Datasheet, PDF (45/90 Pages) Freescale Semiconductor, Inc – K61 Sub-Family Data Sheet

DDR_CLK
DDR_CLK
DDR_CSn, DDR_WE
DDR_CAS, DDR_RAS
DDR_An
DDR_DQS (CL=2.5)
DDR_DQn (CL=2.5)
DDR_DQS (CL=3)
DDR_DQn (CL=3)
tDDRCK
Peripheral operating requirements and behaviors
tDDRCKH
tDDRCKL
CMD
tCMV
tCMH
ROW
COL
CL=2.5
DQS read
preamble
DQS read
postamble
CL=3
RD1 RD2 RD3 RD4
DQS read
preamble
DQS read
postamble
tIH
RD1 RD2 RD3 RD4
tIS
Figure 17. DDR read timing
Figure 18. DDR read timing, DQ vs. DQS
6.4.5 Flexbus Switching Specifications
All processor bus timings are synchronous; input setup/hold and output delay are given in
respect to the rising edge of a reference clock, FB_CLK. The FB_CLK frequency may be
the same as the internal system bus frequency or an integer divider of that frequency.
K61 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
Freescale Semiconductor, Inc.
Preliminary
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