K61P256M120SF3 Datasheet, PDF (43/90 Pages) Freescale Semiconductor, Inc – K61 Sub-Family Data Sheet

Symbol
t_DDRCK
Peripheral operating requirements and behaviors
Table 25. DDR controller — AC timing specifications (continued)
Description
Clock period
• DDR1
• DDR2
• LPDDR
Min.
6.6
6.6
6.6
Max.
12
8
20
Unit
Notes
ns
ns
ns
V_OX-AC
DDRCK AC differential cross point voltage
0.5 x V_{DD_DDR} 0.5 x V_{DD_DDR}
V
• DDR1
– 0.2 V
+ 0.2 V
V
• DDR2
• LPDDR
0.5 x V_{DD_DDR} 0.5 x V_{DD_DDR}
V
– 0.125 V
+ 0.125 V
0.4 x V_{DD_DDR} 0.4 x V_{DD_DDR}
t_DDRCKH
Pulse width high
0.45
0.55
t_DDRCK
3
t_DDRCKL
Pulse width low
0.45
0.55
t_DDRCK
3
t_CMV
Address, DDR_CKE, DDR_CAS, DDR_RAS,
0.5 x t_DDRCK –
—
DDR_WE, DDR_CSn — output valid
1
ns
4
t_CMH
Address, DDR_CKE, DDR_CAS, DDR_RAS,
0.5 x t_DDRCK –
—
ns
DDR_WE, DDR_CSn — output hold
1
t_DQSS
Write command to first DQS latching transition
WL – 0.2 x
WL + 0.2 x
ns
t_DDRCK
t_DDRCK
t_QS
Data and data mask output setup (DQ→DQS)
0.25 x t_DDRCK
—
relative to DQS (DDR write mode)
–1
ns
5, 6
t_QH
Data and data mask output hold (DQS→DQ)
0.25 x t_DDRCK
—
relative to DQS (DDR write mode)
–1
ns
7
t_DQSQ
DQS-DQ skew for DQS and associated DQ
– (0.25 x
0.25 x t_DDRCK
ns
8
signals
t_DDRCK – 1)
–1
1. This is minimum frequency of operation according to JEDEC DDR2 specification.
2. DDR data rate = 2 x DDR clock frequency
3. Pulse width high plus pulse width low cannot exceed min and max clock period.
4. Command output valid should be 1/2 the memory bus clock (t_DDRCK) plus some minor adjustments for process,
temperature, and voltage variations.
5. This specification relates to the required input setup time of DDR memories. The microprocessor's output setup should be
larger than the input setup of the DDR memories. If it is not larger, then the input setup on the memory is in violation.
DDR_DQ[15:8] is relative to DDR_DQS[1]; DDR_DQ[7:0] is relative to DDR_DQS[0].
6. The first data beat is valid before the first rising edge of DQS and after the DQS write preamble. The remaining data beats
are valid for each subsequent DQS edge.
7. This specification relates to the required hold time of DDR memories. DDR_DQ[15:8] is relative to DDR_DQS[1];
DDR_DQ[7:0] is relative to DDR_DQS[0]
8. Data input skew is derived from each DQS clock edge. It begins with a DQS transition and ends when the last data line
becomes valid. This input skew must include DDR memory output skew and system level board skew (due to routing or
other factors).
K61 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
Freescale Semiconductor, Inc.
Preliminary
43