K61P256M120SF3 Datasheet, PDF (42/90 Pages) Freescale Semiconductor, Inc – K61 Sub-Family Data Sheet

Peripheral operating requirements and behaviors
NFC_CEn
NFC_RE
NFC_IOn
NFC_RB
tRC
tRP tREH
tIS
data
data
tRR
tCH
data
Figure 14. Read data latch cycle timing in non-fast mode
NFC_CEn
NFC_RE
NFC_IOn
NFC_RB
tRC
tRP tREH
tIS
data
data
tRR
tCH
data
Figure 15. Read data latch cycle timing in fast mode
6.4.4 DDR controller specifications
The following timing numbers must be followed to properly latch or drive data onto the
DDR memory bus. All timing numbers are relative to the DQS byte lanes.
Table 25. DDR controller — AC timing specifications
Symbol
Description
Frequency of operation
• DDR1
• DDR2
• LPDDR
Min.
83.3
125¹
50
Max.
150
150
150
Unit
MHz
MHz
MHz
Notes
2
Table continues on the next page...
K61 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
42
Preliminary
Freescale Semiconductor, Inc.