K61P256M120SF3 Datasheet, PDF (20/90 Pages) Freescale Semiconductor, Inc – K61 Sub-Family Data Sheet

General
Table 6. Power consumption operating behaviors (continued)
Symbol
I_{DD_LLS}
Description
Low leakage stop mode current at 3.0 V
• @ –40 to 25°C
• @ 70°C
• @ 105°C
Min.
Typ.
Max.
Unit
—
200
TBD
μA
—
TBD
TBD
μA
—
TBD
TBD
μA
I_{DD_VLLS3} Very low-leakage stop mode 3 current at 3.0 V
—
6.5
TBD
μA
• @ –40 to 25°C
—
37.4
TBD
μA
• @ 70°C
—
148.3
TBD
μA
• @ 105°C
I_{DD_VLLS2} Very low-leakage stop mode 2 current at 3.0 V
—
3.4
TBD
μA
• @ –40 to 25°C
—
13.4
TBD
μA
• @ 70°C
—
58.5
TBD
μA
• @ 105°C
I_{DD_VLLS1} Very low-leakage stop mode 1 current at 3.0 V
—
2.9
TBD
μA
• @ –40 to 25°C
—
9.8
TBD
μA
• @ 70°C
—
44.7
TBD
μA
• @ 105°C
I_{DD_VBAT}
Average current when CPU is not accessing
RTC registers at 3.0 V
• @ –40 to 25°C
• @ 70°C
• @ 105°C
—
0.91
1.1
μA
—
1.5
1.85
μA
—
4.3
4.3
μA
Notes
8
#new-
reference/
llsramn
9
1. The analog supply current is the sum of the active or disabled current for each of the analog modules on the device. See
each module's specification for its supply current.
2. 120 MHz core and system clock, 60 MHz bus, 30 MHz FlexBus clock, and 20 MHz flash clock. MCG configured for PEE
mode. All peripheral clocks disabled.
3. 120 MHz core and system clock, 60 MHz bus, 50 MHz FlexBus clock, and 20 MHz flash clock. MCG configured for PEE
mode. All peripheral clocks enabled, but peripherals are not in active operation.
4. 25 MHz core and system clock, 25 MHz bus clock, and 12.5 MHz FlexBus and flash clock. MCG configured for FEI mode.
5. 4 MHz core, system, 2 MHz FlexBus, and 2 MHz bus clock and 1 MHz flash clock. MCG configured for BLPE mode. All
peripheral clocks disabled.
6. 4 MHz core, system, 2 MHz FlexBus, and 2 MHz bus clock and 1 MHz flash clock. MCG configured for BLPE mode. All
peripheral clocks disabled.
7. 4 MHz core, system, 2 MHz FlexBus, and 2 MHz bus clock and 1 MHz flash clock. MCG configured for BLPE mode. All
peripheral clocks disabled.
8. Data reflects devices with 128 KB of RAM. For devices with 64 KB of RAM, power consumption is reduced by 2 μA.
9. Includes 32kHz oscillator current and RTC operation.
5.2.5.1 Diagram: Typical IDD_RUN operating behavior
The following data was measured under these conditions:
K61 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
20
Preliminary
Freescale Semiconductor, Inc.