K61P256M120SF3 Datasheet, PDF (18/90 Pages) Freescale Semiconductor, Inc – K61 Sub-Family Data Sheet

General
Table 4. Voltage and current operating behaviors (continued)
Symbol Description
I_OZ
Hi-Z (off-state) leakage current (per pin)
I_{OZ_DDR} Hi-Z (off-state) leakage current (per DDR pin)
I_{OZ_Tamper} Hi-Z (off-state) leakage current (per Tamper pin)
R_PU
Internal pullup resistors
R_PD
Internal pulldown resistors
R_{PU_Tamper} Internal pullup resistors (per Tamper pin)
R_{PD_Tamper} Internal pulldown resistors (per Tamper pin)
R_ODT
On-die termination (ODT) resistance for DDR2
• R_tt1(eff) - 75 Ω
• R_tt2(eff) - 150 Ω
Min.
Max.
Unit
—
1
μA
—
1
μA
—
1
μA
20
50
kΩ
20
50
kΩ
20
50
kΩ
20
50
kΩ
60
90
Ω
120
180
Ω
1. Measured at VDD=3.6V
2. Measured at V_DD supply voltage = V_DD min and Vinput = V_SS
3. Measured at V_DD supply voltage = V_DD min and Vinput = V_DD
Notes
2
3
5.2.4 Power mode transition operating behaviors
All specifications except t_POR, and VLLSx→RUN recovery times in the following table
assume this clock configuration:
• CPU and system clocks = FEI 100 MHz
• Bus clock = 50 MHz
• FlexBus clock = 50 MHz
• Flash clock = 25 MHz
Symbol
t_POR
Table 5. Power mode transition operating behaviors
Description
Min.
Max.
Unit
After a POR event, amount of time from the point V_DD
—
300
μs
reaches 1.71 V to execution of the first instruction
across the operating temperature range of the chip.
• VLLS1 → RUN
—
126
μs
Notes
1
• VLLS2 → RUN
• VLLS3 → RUN
• LLS → RUN
—
82
μs
—
82
μs
—
5.0
μs
Table continues on the next page...
K61 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
18
Preliminary
Freescale Semiconductor, Inc.