K61P256M120SF3 Datasheet, PDF (14/90 Pages) Freescale Semiconductor, Inc – K61 Sub-Family Data Sheet

General
Table 1. Voltage and current operating requirements (continued)
Symbol
V_{IL_DDR}
Description
Input low voltage (DDR pins)
• DDR1
• DDR2
• LPDDR
V_{IH_Tamper}
Tamper input high voltage
• 2.7 V ≤ V_BAT ≤ 3.6 V
• 1.7 V ≤ V_BAT ≤ 2.7 V
Min.
Max.
—
V_{REF_DDR} –
—
0.15
—
V_{REF_DDR} –
0.125
0.3 ×
V_{DD_DDR}
0.7 × V_BAT
—
0.75 × V_BAT
—
Unit
V
V
V
V
V
Notes
V_{IL_Tamper}
Tamper input low voltage
• 2.7 V ≤ V_BAT ≤ 3.6 V
• 1.7 V ≤ V_BAT ≤ 2.7 V
—
0.35 × V_BAT
V
—
0.3 × V_BAT
V
V_HYS
Input hysteresis (digital pins except Tamper pins and 0.06 × V_DD
—
V
DDR pins)
V_{HYS_Tamper} Input hysteresis (Tamper pins)
0.06 × V_BAT
—
V
I_ICDIO
Digital pin (except Tamper pins and DDR pins)
negative DC injection current — single pin
1
-5
—
mA
• V_IN < V_SS-0.3V
I_{ICDIO_DDR} DDR pin negative DC injection current -- single pin
TBD
TBD
mA
• TBD
I_{ICDIO_Tamper} Tamper pin negative DC injection current — single pin
-0.2
—
mA
• V_IN < V_SS-0.3V
—
2.0
mA
• V_IN > V_BAT
I_ICAIO
Analog², EXTAL0/XTAL0, and EXTAL1/XTAL1 pin DC
injection current — single pin
3
mA
• V_IN < V_SS-0.3V (Negative current injection)
-5
—
• V_IN > V_DD+0.3V (Positive current injection)
—
+5
I_ICcont
Contiguous pin DC injection current —regional limit,
includes sum of negative injection currents or sum of
positive injection currents of 16 contiguous pins
• Negative current injection
-25
—
mA
• Positive current injection
—
+25
V_RAM
V_DD (V_{DD_INT}) voltage required to retain RAM
1.2
—
V
V_RFVBAT V_BAT voltage required to retain the VBAT register file V_{POR_VBAT}
—
V
1. All 5 V tolerant digital I/O pins are internally clamped to V_SS through a ESD protection diode. There is no diode connection
to V_DD. If V_IN greater than V_{DIO_MIN} (=V_SS-0.3V) is observed, then there is no need to provide current limiting resistors at
K61 Sub-Family Data Sheet Data Sheet, Rev. 3, 2/2012.
14
Preliminary
Freescale Semiconductor, Inc.