MC9S12K Datasheet, PDF(76/126 Page) Freescale Semiconductor, Inc

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MC9S12K Datasheet, PDF (76/126 Pages) Freescale Semiconductor, Inc – Microcontrollers

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Device User Guide â 9S12KT256DGV1/D V01.09

Section 5 Resets and Interrupts

5.1 Overview

Consult the Exception Processing section of the CPU12 Reference Manual for information on resets and

interrupts. Both local masking and CCR masking are included as listed in Table 5-1. System resets can

be generated through external control of the RESET pin, through the clock and reset generator module

CRG or through the low voltage reset (LVR) generator of the voltage regulator module. Refer to the CRG

and VREG Block Guides for detailed information on reset generation.

5.2 Vectors

5.2.1 Vector Table

(Table 5-1) lists interrupt sources and vectors in default order of priority.

Vector Address

$FFFE, $FFFF

$FFFC, $FFFD

$FFFA, $FFFB

$FFF8, $FFF9

$FFF6, $FFF7

$FFF4, $FFF5

$FFF2, $FFF3

$FFF0, $FFF1

$FFEE, $FFEF

$FFEC, $FFED

$FFEA, $FFEB

$FFE8, $FFE9

$FFE6, $FFE7

$FFE4, $FFE5

$FFE2, $FFE3

$FFE0, $FFE1

$FFDE, $FFDF

$FFDC, $FFDD

$FFDA, $FFDB

$FFD8, $FFD9

$FFD6, $FFD7

$FFD4, $FFD5

$FFD2, $FFD3

Table 5-1 Interrupt Vector Locations

Interrupt Source

CCR

Mask

Local Enable

External Reset, Power On Reset or Low

Voltage Reset (see CRG Flags Register None

to determine reset source)

None

Clock Monitor fail reset

None

PLLCTL (CME, FCME)

COP failure reset

None

COP rate select

Unimplemented instruction trap

None

SWI

None

XIRQ

X-Bit

None

IRQ

I-Bit

IRQCR (IRQEN)

Real Time Interrupt

I-Bit

CRGINT (RTIE)

Standard Timer channel 0

I-Bit

TIE (C0I)

Standard Timer channel 1

I-Bit

TIE (C1I)

Standard Timer channel 2

I-Bit

TIE (C2I)

Standard Timer channel 3

I-Bit

TIE (C3I)

Standard Timer channel 4

I-Bit

TIE (C4I)

Standard Timer channel 5

I-Bit

TIE (C5I)

Standard Timer channel 6

I-Bit

TIE (C6I)

Standard Timer channel 7

I-Bit

TIE (C7I)

Standard Timer overï¬ow

I-Bit

TSCR2 (TOI)

Pulse accumulator overï¬ow

I-Bit

PACTL (PAOVI)

Pulse accumulator input edge

I-Bit

PACTL (PAI)

SPI0

I-Bit

SPICR1 (SPIE, SPTIE)

SCI0

I-Bit

SCICR2

(TIE, TCIE, RIE, ILIE)

SCI1

I-Bit

SCICR2

(TIE, TCIE, RIE, ILIE)

ATD0

I-Bit

ATDCTL2 (ASCIE)

HPRIO Value

to Elevate

$F2

$F0

$EE

$EC

$EA

$E8

$E6

$E4

$E2

$E0

$DE

$DC

$DA

$D8

$D6

$D4

$D2

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