MC9S12K Datasheet, PDF (2/126 Pages) Freescale Semiconductor, Inc – Microcontrollers

Device User Guide — 9S12KT256DGV1/D V01.09
Revision History
Version Revision
Number Date
01.00 16 JUL 02
01.01 22 NOV 02
01.02
01.03
01.04
15 JAN 03
13 JUN 03
18 JUN 03
01.05 14 NOV 03
01.06
01.07
10 FEB 04
13 MAY 04
01.08 20 JUL 04
01.09 9 SEP 04
Author
Description of Changes
Original Version.
Change load cap value on VDD and VDDPLL.
Correct expanded bus timing from 20MHz to 25 MHz.
Move ATD interrupt vector from $ffd0 to $ffd2.
Change PWeh and tDSW parameter in external bus timing.
Expand to a K-Family SoC Guide and include 9S12KT256.
Replace 16-channel ATD with two 8-channel ATDs for 9S12KT256.
Changed to a Device User Guide and added Document number.
Updated Table A-17 Oscillator Characteristics.
Replaced XCLKS with PE7 for Clock Selection diagrams.
Added CTRL to Table 2-1 Signal Properties.
Replaced Burst programming with Row Programming in NVM
electricals.
Changed Digital logic to Internal Logic.
Added LRAE bootloader information.
Changed PW_EL, PW_EH, t_DSW, t_ACCE, t_NAD, t_NAV, t_RWV, t_LSV, t_NOV,
t_P0V and t_P1V in the external bus timing.
Added voltage regulator characteristics.
Updated Table A-7 3.3V I/O Characteristics.
Updated Table A-16 NVM Timing Characteristics.
Corrected A.6.1.2 Row Programming time t_bwpgm equation
Expanded K-family to include 9S12KC128, 9S12KC64, 9S12KL128
and 9S12KL64.
Updated osciilator start up time and supply current characteristics.
Added ATDCTL0 and ATDCTL1 register bits to Sec 1.7.
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