MC9S12K Datasheet, PDF (113/126 Pages) Freescale Semiconductor, Inc – Microcontrollers

Device User Guide — 9S12KT256DGV1/D V01.09
SS¹
(OUTPUT)
SCK
(CPOL = 0)
(OUTPUT)
SCK
(CPOL = 1)
(OUTPUT)
MISO
(INPUT)
1
2
4
4
5
6
MSB IN²
12
11
BIT 6 . . . 1
9
MOSI
(OUTPUT)
PORT DATA
10
MASTER MSB OUT² BIT 6 . . . 1
1.If configured as output
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
11
3
12
LSB IN
MASTER LSB OUT PORT DATA
Figure A-6 SPI Master Timing (CPHA =1)
Table A-22 SPI Master Mode Timing Characteristics
Conditions are shown in Table A-4 unless otherwise noted, CLOAD = 200pF on all outputs
Num C
Rating
Symbol
Min
Typ
1 P Operating Frequency
f_op
DC
1 P SCK Period
t_sck
4
2 D Enable Lead Time
t_lead
1/2
3 D Enable Lag Time
4 D Clock (SCK) High or Low Time
t_lag
t_wsck
1/2
t_bus − 30
5 D Data Setup Time (Inputs)
t_su
25
6 D Data Hold Time (Inputs)
t_hi
0
9 D Data Valid (after SCK Edge)
t_v
10 D Data Hold Time (Outputs)
t_ho
0
11 D Rise Time Inputs and Outputs
t_r
12 D Fall Time Inputs and Outputs
t_f
Max
1/4
2048
—
1024 t_bus
25
25
25
Unit
f_bus
t_bus
t_sck
t_sck
ns
ns
ns
ns
ns
ns
ns
Freescale Semiconductor
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