MC9S12K Datasheet, PDF (62/126 Pages) Freescale Semiconductor, Inc – Microcontrollers

Device User Guide — 9S12KT256DGV1/D V01.09
2.3.10 PB[7:0] / ADDR[7:0] / DATA[7:0] — Port B I/O Pins
PB7-PB0 are general purpose input or output pins. In MCU expanded modes of operation, these pins are
used for the multiplexed external address and data bus.
2.3.11 PE7 / NOACC / XCLKS — Port E I/O Pin 7
PE7 is a general purpose input or output pin. During MCU expanded modes of operation, the NOACC
signal, when enabled, is used to indicate that the current bus cycle is an unused or “free” cycle. This signal
will assert when the CPU is not using the bus.
The XCLKS is an input signal which controls whether a crystal in combination with the internal Loop
Controlled Pierce (low power) oscillator is used or whether Full Swing Pierce oscillator/external clock
circuitry is used. The state of this pin is latched at the rising edge of RESET. If the input is a logic low the
EXTAL pin is configured for an external clock drive or Full Swing Pierce Oscillator. If input is a logic
high a Loop Controlled Pierce oscillator circuit is configured on EXTAL and XTAL. Since this pin is an
input with a pull-up device during reset, if the pin is left floating, the default configuration is a Loop
Controlled Pierce oscillator circuit on EXTAL and XTAL.
Table 2-3 Clock selection based on PE7 during reset
PE7
1
0
Description
Loop Controlled Pierce Oscillator selected
Full Swing Pierce Oscillator or external clock selected
EXTAL
MCU
XTAL
C₇
Crystal or
ceramic resonator
C₈
VSSPLL
Figure 2-5 Loop Controlled Pierce Oscillator Connections (PE7=1)
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