MC9S12K Datasheet, PDF(57/126 Page) Freescale Semiconductor, Inc

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MC9S12K Datasheet, PDF (57/126 Pages) Freescale Semiconductor, Inc – Microcontrollers

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2.2 Signal Properties Summary

Device User Guide â 9S12KT256DGV1/D V01.09

(Table 2-1) summarizes the pin functionality. Signals shown in bold are not available in the 80 pin

package. (Table 2-2) summarizes the power and ground pins.

Table 2-1 Signal Properties

Pin Name

Function 1

EXTAL

XTAL

RESET

TEST

VREGEN

XFC

BKGD

PAD[15:8]

PAD[7:0]

PA[7:0]

PB[7:0]

PE7

PE6

PE5

PE4

PE3

PE2

PE1

PE0

PH7

Pin Name

Function 2

TAGHI

AN[15:8]

AN[7:0]

ADDR[15:8]/

DATA[15:8]

ADDR[7:0]/

DATA[7:0]

NOACC

IPIPE1

IPIPE0

ECLK

LSTRB

R/W

IRQ

XIRQ

KWH7

Pin Name Pin Name Powered

Function 3 Function 4 by

MODC

VDDPLL

VDDR

VDDX

VDDPLL

VDDR

AN1[7:0]1

VDDA

AN0[7:0]1

VDDA

XCLKS

MODB

MODA

TAGLO

SS2

VDDR

Internal Pull

Resistor

CTRL

Reset

State

None None

Always

None None

Description

Oscillator Pins

External Reset

Test Input

Voltage Regulator Enable Input

PLL Loop Filter

Background Debug, Tag High, Mode

Input

Port AD Input, Analog Inputs of ATD

in MC9S12KG128(64)(32),

MC9S12KL128(64) and

MC9S12KC128(64); Analog Inputs of

ATD1 in MC9S12KT256 and

MC9S12KG256

Port AD Input, Analog Inputs of ATD in

MC9S12KG128(64)(32),

MC9S12KL128(64) and

MC9S12KC128(64); Analog Inputs of

ATD0 in MC9S12KT256 and

MC9S12KG256

PUCR Disabled Port A I/O, Multiplexed Address/Data

PUCR Disabled Port B I/O, Multiplexed Address/Data

PUCR

Up Port E I/O, Access, Clock Select

While RESET

pin is low:

Down

Port E I/O, Pipe Status, Mode Input

While RESET

pin is low:

Down

Port E I/O, Pipe Status, Mode Input

PUCR

Up Port E I/O, Bus Clock Output

PUCR

Up Port E I/O, Byte Strobe, Tag Low

PUCR

Up Port E I/O, R/W in expanded modes

Always Up

Port E Input, Maskable Interrupt

Port E Input, Non Maskable Interrupt

PERH/

PPSH

Disabled Port H I/O, Interrupt, SS of SPI2

Freescale Semiconductor

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